riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-02-05	qdev: use device_class_set_parent_realize/unrealize/reset()	Philippe Mathieu-Daudé	1	-3/+2
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	3	-7/+7
2018-01-16	mips: Tweak location of ';' in macros	Eric Blake	1	-16/+18
2017-12-29	tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*	Richard Henderson	1	-1/+1
2017-10-30	Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...	Peter Maydell	4	-29/+13
2017-10-27	mips: malta/boston: replace cpu_model with cpu_type	Igor Mammedov	4	-29/+13
2017-10-27	Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging	Peter Maydell	1	-1/+1
2017-10-26	tcg: Avoid setting tcg_initialize if !CONFIG_TCG	Richard Henderson	1	-0/+2
2017-10-25	disas: Remove unused flags arguments	Richard Henderson	1	-1/+1
2017-10-24	tcg: Initialize cpu_env generically	Richard Henderson	1	-4/+0
2017-10-24	tcg: define tcg_init_ctx and make tcg_ctx a pointer	Emilio G. Cota	1	-1/+1
2017-10-24	tcg: convert tb->cflags reads to tb_cflags(tb)	Emilio G. Cota	1	-13/+13
2017-10-24	qom: Introduce CPUClass.tcg_initialize	Richard Henderson	2	-11/+1
2017-10-16	linux-user: Tidy and enforce reserved_va initialization	Richard Henderson	1	-1/+5
2017-10-10	tcg: remove addr argument from lookup_tb_ptr	Emilio G. Cota	1	-2/+2
2017-10-09	qom/cpu: move cpu_model null check to cpu_class_by_name()	Philippe Mathieu-Daudé	1	-4/+0
2017-09-21	mips: Improve macro parenthesization	Eric Blake	1	-28/+28
2017-09-21	mips: replace cpu_mips_init() with cpu_generic_init()	Igor Mammedov	2	-19/+1
2017-09-21	mips: MIPSCPU model subclasses	Igor Mammedov	5	-64/+117
2017-09-21	mips: call cpu_mips_realize_env() from mips_cpu_realizefn()	Philippe Mathieu-Daudé	2	-1/+3
2017-09-21	mips: split cpu_mips_realize_env() out of cpu_mips_init()	Philippe Mathieu-Daudé	2	-7/+13
2017-09-21	mips: introduce internal.h and cleanup cpu.h	Philippe Mathieu-Daudé	11	-353/+372
2017-09-21	mips: move hw/mips/cputimer.c to target/mips/	Philippe Mathieu-Daudé	2	-1/+165
2017-09-19	target/mips: Convert VM clock update prints to warn_report	Alistair Francis	1	-3/+3
2017-09-19	Convert single line fprintf(.../n) to warn_report()	Alistair Francis	1	-2/+2
2017-08-02	target/mips: Fix RDHWR CC with icount	James Hogan	1	-0/+11
2017-08-02	target/mips: Drop redundant gen_io_start/stop()	James Hogan	1	-8/+0
2017-08-02	target/mips: Use BS_EXCP where interrupts are expected	James Hogan	1	-13/+34
2017-08-02	target-mips: apply CP0.PageMask before writing into TLB entry	Leon Alrae	1	-2/+3
2017-08-02	mips: Add KVM T&E segment support for TCG	James Hogan	2	-4/+4
2017-08-02	mips: Improve segment defs for KVM T&E guests	James Hogan	1	-12/+11
2017-08-02	target-mips: Don't stop on [d]mtc0 DESAVE/KScratch	James Hogan	1	-4/+0
2017-07-31	docs: fix broken paths to docs/devel/tracing.txt	Philippe Mathieu-Daudé	1	-1/+1
2017-07-21	target/mips: Enable CP0_EBase.WG on MIPS64 CPUs	James Hogan	1	-0/+2
2017-07-21	target/mips: Add EVA support to P5600	James Hogan	1	-6/+8
2017-07-20	target/mips: Implement segmentation control	James Hogan	1	-39/+152
2017-07-20	target/mips: Add segmentation control registers	James Hogan	5	-2/+150
2017-07-20	target/mips: Add an MMU mode for ERL	James Hogan	2	-4/+23
2017-07-20	target/mips: Abstract mmu_idx from hflags	James Hogan	3	-4/+10
2017-07-20	target/mips: Check memory permissions with mem_idx	James Hogan	1	-8/+9
2017-07-20	target/mips: Decode microMIPS EVA load & store instructions	James Hogan	1	-4/+115
2017-07-20	target/mips: Decode MIPS32 EVA load & store instructions	James Hogan	1	-0/+106
2017-07-20	target/mips: Prepare loads/stores for EVA	James Hogan	1	-35/+42
2017-07-20	target/mips: Add CP0_Ebase.WG (write gate) support	James Hogan	6	-15/+31
2017-07-20	target/mips: Weaken TLB flush on UX,SX,KX,ASID changes	James Hogan	2	-2/+2
2017-07-20	target/mips: Fix TLBWI shadow flush for EHINV,XI,RI	James Hogan	1	-2/+10
2017-07-20	target/mips: Fix MIPS64 MFC0 UserLocal on BE host	James Hogan	1	-2/+3
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	1	-3/+2
2017-07-17	target/mips: optimize WSBH, DSBH and DSHD	Aurelien Jarno	1	-6/+12
2017-07-17	mips: set CP0 Debug DExcCode for SDBBP instruction	Pavel Dovgalyuk	1	-0/+2