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| author | Aurelien Jarno <aurelien@aurel32.net> | 2017-06-23 12:41:16 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2017-07-17 16:48:21 +0200 |
| commit | 06a57e5cc7ee5292a4915117ebf951e310a28264 (patch) | |
| tree | c5cb3dcf67a981a57d81f7afc219d5a943d8b265 /target/mips | |
| parent | c6c2c0fc32362ba234ae3bdad1a55c2d6aefaa12 (diff) | |
| download | qemu-06a57e5cc7ee5292a4915117ebf951e310a28264.zip qemu-06a57e5cc7ee5292a4915117ebf951e310a28264.tar.gz qemu-06a57e5cc7ee5292a4915117ebf951e310a28264.tar.bz2 | |
target/mips: optimize WSBH, DSBH and DSHD
Use the same mask to avoid having to load two different constants.
Suggested-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/translate.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index befb87f..fe44f2f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4572,12 +4572,14 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) case OPC_WSBH: { TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_const_tl(0x00FF00FF); tcg_gen_shri_tl(t1, t0, 8); - tcg_gen_andi_tl(t1, t1, 0x00FF00FF); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); - tcg_gen_andi_tl(t0, t0, ~0x00FF00FF); tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t2); tcg_temp_free(t1); tcg_gen_ext32s_tl(cpu_gpr[rd], t0); } @@ -4592,27 +4594,31 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) case OPC_DSBH: { TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL); tcg_gen_shri_tl(t1, t0, 8); - tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); - tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t2); tcg_temp_free(t1); } break; case OPC_DSHD: { TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL); tcg_gen_shri_tl(t1, t0, 16); - tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 16); - tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL); tcg_gen_or_tl(t0, t0, t1); tcg_gen_shri_tl(t1, t0, 32); tcg_gen_shli_tl(t0, t0, 32); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t2); tcg_temp_free(t1); } break; |