riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-08-02	target/mips: Fix RDHWR CC with icount	James Hogan	1	-0/+11
2017-08-02	target/mips: Drop redundant gen_io_start/stop()	James Hogan	1	-8/+0
2017-08-02	target/mips: Use BS_EXCP where interrupts are expected	James Hogan	1	-13/+34
2017-08-02	target-mips: apply CP0.PageMask before writing into TLB entry	Leon Alrae	1	-2/+3
2017-08-02	mips: Add KVM T&E segment support for TCG	James Hogan	2	-4/+4
2017-08-02	mips: Improve segment defs for KVM T&E guests	James Hogan	1	-12/+11
2017-08-02	target-mips: Don't stop on [d]mtc0 DESAVE/KScratch	James Hogan	1	-4/+0
2017-07-31	docs: fix broken paths to docs/devel/tracing.txt	Philippe Mathieu-Daudé	1	-1/+1
2017-07-21	target/mips: Enable CP0_EBase.WG on MIPS64 CPUs	James Hogan	1	-0/+2
2017-07-21	target/mips: Add EVA support to P5600	James Hogan	1	-6/+8
2017-07-20	target/mips: Implement segmentation control	James Hogan	1	-39/+152
2017-07-20	target/mips: Add segmentation control registers	James Hogan	5	-2/+150
2017-07-20	target/mips: Add an MMU mode for ERL	James Hogan	2	-4/+23
2017-07-20	target/mips: Abstract mmu_idx from hflags	James Hogan	3	-4/+10
2017-07-20	target/mips: Check memory permissions with mem_idx	James Hogan	1	-8/+9
2017-07-20	target/mips: Decode microMIPS EVA load & store instructions	James Hogan	1	-4/+115
2017-07-20	target/mips: Decode MIPS32 EVA load & store instructions	James Hogan	1	-0/+106
2017-07-20	target/mips: Prepare loads/stores for EVA	James Hogan	1	-35/+42
2017-07-20	target/mips: Add CP0_Ebase.WG (write gate) support	James Hogan	6	-15/+31
2017-07-20	target/mips: Weaken TLB flush on UX,SX,KX,ASID changes	James Hogan	2	-2/+2
2017-07-20	target/mips: Fix TLBWI shadow flush for EHINV,XI,RI	James Hogan	1	-2/+10
2017-07-20	target/mips: Fix MIPS64 MFC0 UserLocal on BE host	James Hogan	1	-2/+3
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	1	-3/+2
2017-07-17	target/mips: optimize WSBH, DSBH and DSHD	Aurelien Jarno	1	-6/+12
2017-07-17	mips: set CP0 Debug DExcCode for SDBBP instruction	Pavel Dovgalyuk	1	-0/+2
2017-07-11	target/mips: fix msa copy_[s\|u]_df rd = 0 corner case	Miodrag Dinic	1	-2/+6
2017-07-04	vcpu_dirty: share the same field in CPUState for all accelerators	Sergio Andres Gomez Del Real	1	-2/+2
2017-06-05	target/mips: optimize indirect branches	Aurelien Jarno	1	-1/+1
2017-06-05	target/mips: optimize cross-page direct jumps in softmmu	Aurelien Jarno	1	-1/+1
2017-03-20	target/mips: fix delay slot detection in gen_msa_branch()	Yongbok Kim	1	-1/+1
2017-03-20	target-mips: replace few LOG_DISAS() with trace points	Philippe Mathieu-Daudé	2	-14/+16
2017-03-20	target-mips: replace break by goto cp0_unimplemented	Philippe Mathieu-Daudé	1	-44/+44
2017-03-20	target-mips: log bad coprocessor0 register accesses with LOG_UNIMP	Philippe Mathieu-Daudé	1	-6/+6
2017-03-20	target-mips: remove old & unuseful comments	Philippe Mathieu-Daudé	1	-4/+0
2017-03-20	target-mips: fix compiler warnings (clang 5)	Philippe Mathieu-Daudé	1	-4/+12
2017-03-09	target/mips: hold BQL for timer interrupts	Yongbok Kim	1	-3/+18
2017-03-03	KVM: do not use sigtimedwait to catch SIGBUS	Paolo Bonzini	1	-6/+0
2017-03-03	KVM: remove kvm_arch_on_sigbus	Paolo Bonzini	1	-6/+0
2017-02-21	target-mips: Provide function to test if a CPU supports an ISA	Paul Burton	2	-0/+11
2017-01-24	migration: extend VMStateInfo	Jianjun Duan	1	-4/+10
2017-01-20	Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging	Peter Maydell	1	-0/+5
2017-01-16	stubs: remove stubs/kvm.c	Paolo Bonzini	1	-0/+5
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	3	-8/+8
2017-01-13	qom/cpu: move tlb_flush to cpu_common_reset	Alex Bennée	2	-2/+4
2017-01-10	target-mips: Use clz opcode	Richard Henderson	3	-36/+16
2017-01-10	target-mips: Use the new extract op	Richard Henderson	1	-7/+5
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	19	-0/+38839