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authorAlex Bennée <alex.bennee@linaro.org>2016-11-14 14:19:17 +0000
committerAlex Bennée <alex.bennee@linaro.org>2017-01-13 14:24:31 +0000
commit1f5c00cfdb8114c1e3a13426588ceb64f82c9ddb (patch)
treea2cdd1a75d613b7509e7968cd973c30d383c1186 /target/mips
parentb6c08970bc989bfddcf830684ea7a96b7a4d62a7 (diff)
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qom/cpu: move tlb_flush to cpu_common_reset
It is a common thing amongst the various cpu reset functions want to flush the SoftMMU's TLB entries. This is done either by calling tlb_flush directly or by way of a general memset of the CPU structure (sometimes both). This moves the tlb_flush call to the common reset function and additionally ensures it is only done for the CONFIG_SOFTMMU case and when tcg is enabled. In some target cases we add an empty end_of_reset_fields structure to the target vCPU structure so have a clear end point for any memset which is resetting value in the structure before CPU_COMMON (where the TLB structures are). While this is a nice clean-up in general it is also a precursor for changes coming to cputlb for MTTCG where the clearing of entries can't be done arbitrarily across vCPUs. Currently the cpu_reset function is usually called from the context of another vCPU as the architectural power up sequence is run. By using the cputlb API functions we can ensure the right behaviour in the future. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/cpu.c3
-rw-r--r--target/mips/cpu.h3
2 files changed, 4 insertions, 2 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 65ca607..1bb66b7 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -100,8 +100,7 @@ static void mips_cpu_reset(CPUState *s)
mcc->parent_reset(s);
- memset(env, 0, offsetof(CPUMIPSState, mvp));
- tlb_flush(s, 1);
+ memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
cpu_state_reset(env);
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 5182dc7..3146a60 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -607,6 +607,9 @@ struct CPUMIPSState {
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
int insn_flags; /* Supported instruction set */
+ /* Fields up to this point are cleared by a CPU reset */
+ struct {} end_reset_fields;
+
CPU_COMMON
/* Fields from here on are preserved across CPU reset. */