riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-08-27	opentitan: Rename memmap enum constants	Eduardo Habkost	1	-19/+19
2020-08-25	hw/riscv: virt: Allow creating multiple NUMA sockets	Anup Patel	1	-2/+7
2020-08-25	hw/riscv: spike: Allow creating multiple NUMA sockets	Anup Patel	1	-2/+9
2020-08-25	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	Anup Patel	1	-0/+113
2020-08-25	hw/riscv: Allow creating multiple instances of PLIC	Anup Patel	1	-5/+7
2020-08-25	hw/riscv: Allow creating multiple instances of CLINT	Anup Patel	1	-3/+4
2020-08-21	hw/riscv: sifive_u: Add a dummy L2 cache controller device	Bin Meng	1	-0/+4
2020-07-13	riscv: Add opensbi firmware dynamic support	Atish Patra	2	-1/+62
2020-07-13	RISC-V: Copy the fdt in dram instead of ROM	Atish Patra	1	-1/+3
2020-07-13	riscv: Unify Qemu's reset vector code path	Atish Patra	1	-0/+2
2020-06-19	hw/riscv: sifive_u: Add a dummy DDR memory controller device	Bin Meng	1	-0/+1
2020-06-19	hw/riscv: sifive_u: Support different boot source per MSEL pin state	Bin Meng	1	-0/+6
2020-06-19	hw/riscv: sifive_u: Add a new property msel for MSEL pin state	Bin Meng	1	-0/+1
2020-06-19	hw/riscv: sifive_u: Hook a GPIO controller	Bin Meng	1	-0/+19
2020-06-19	hw/riscv: sifive_gpio: Add a new 'ngpio' property	Bin Meng	1	-0/+3
2020-06-19	hw/riscv: sifive_gpio: Clean up the codes	Bin Meng	1	-3/+4
2020-06-19	riscv/opentitan: Connect the UART device	Alistair Francis	1	-0/+13
2020-06-19	riscv/opentitan: Connect the PLIC device	Alistair Francis	1	-0/+3
2020-06-19	sifive_e: Support the revB machine	Alistair Francis	1	-0/+1
2020-06-15	riscv: Fix type of SiFive[EU]SocState, member parent_obj	Markus Armbruster	2	-2/+2
2020-06-03	riscv: Initial commit of OpenTitan machine	Alistair Francis	1	-0/+68
2020-06-03	riscv/boot: Add a missing header include	Alistair Francis	1	-0/+1
2020-06-03	riscv: sifive_e: Manually define the machine	Alistair Francis	1	-0/+4
2020-06-03	hw/riscv: spike: Remove deprecated ISA specific machines	Alistair Francis	1	-4/+2
2020-04-29	hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()	Anup Patel	1	-2/+4
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u machine	Bin Meng	1	-0/+1
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u SoC	Alistair Francis	1	-0/+2
2020-02-27	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	Anup Patel	1	-1/+2
2020-02-10	riscv: virt: Use Goldfish RTC device	Anup Patel	1	-0/+2
2019-11-25	hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()	Zhuang, Siwei (Data61, Kensington NSW)	1	-1/+2
2019-10-28	riscv/virt: Add the PFlash CFI01 device	Alistair Francis	1	-0/+3
2019-10-28	riscv/virt: Manually define the machine	Alistair Francis	1	-1/+6
2019-10-28	riscv/sifive_u: Add the start-in-flash property	Alistair Francis	1	-0/+2
2019-10-28	riscv/sifive_u: Manually define the machine	Alistair Francis	1	-1/+6
2019-10-28	riscv/sifive_u: Add QSPI memory region	Alistair Francis	1	-0/+1
2019-10-28	riscv/sifive_u: Add L2-LIM cache memory	Alistair Francis	1	-0/+1
2019-10-28	riscv: hw: Drop "clock-frequency" property of cpu nodes	Bin Meng	3	-9/+0
2019-09-17	riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet	Bin Meng	1	-2/+1
2019-09-17	riscv: sifive_u: Fix broken GEM support	Bin Meng	1	-1/+2
2019-09-17	riscv: sifive_u: Instantiate OTP memory with a serial number	Bin Meng	1	-0/+3
2019-09-17	riscv: sifive: Implement a model for SiFive FU540 OTP	Bin Meng	1	-0/+80
2019-09-17	riscv: sifive_u: Update UART base addresses and IRQs	Bin Meng	1	-2/+2
2019-09-17	riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes	Bin Meng	1	-0/+10
2019-09-17	riscv: sifive_u: Add PRCI block to the SoC	Bin Meng	1	-0/+3
2019-09-17	riscv: sifive_u: Generate hfclk and rtcclk nodes	Bin Meng	1	-0/+2
2019-09-17	riscv: sifive: Implement PRCI model for FU540	Bin Meng	1	-0/+81
2019-09-17	riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC	Bin Meng	1	-1/+5
2019-09-17	riscv: sifive_u: Set the minimum number of cpus to 2	Bin Meng	1	-0/+2
2019-09-17	riscv: hart: Add a "hartid-base" property to RISC-V hart array	Bin Meng	1	-0/+1
2019-09-17	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	Bin Meng	3	-12/+33