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path: root/include/hw/riscv
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2025-07-04hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototypeHuang Borong1-0/+68
2025-06-10hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]ClassZhenzhong Duan1-4/+2
2025-05-19hw/riscv: Configurable MPFS CLINT timebase freqSebastian Huber1-0/+1
2025-05-19hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structureSunil V L1-0/+1
2025-01-19target/riscv: Handle Smrnmi interrupt and exceptionTommy Wu1-0/+4
2024-12-21Merge tag 'exec-20241220' of https://github.com/philmd/qemu into stagingStefan Hajnoczi1-1/+1
2024-12-20include: Rename sysemu/ -> system/Philippe Mathieu-Daudé1-1/+1
2024-12-20hw/riscv: Add the checking if DTB overlaps to kernel or initrdJim Shu1-0/+3
2024-12-20hw/riscv: Add a new struct RISCVBootInfoJim Shu1-8/+17
2024-12-20hw/riscv: Support to load DTB after 3GB memory on 64-bit system.Jim Shu1-1/+1
2024-12-20hw/riscv/riscv-iommu: implement reset protocolDaniel Henrique Barboza1-2/+4
2024-12-20hw/riscv/virt: Add IOMMU as platform device if the option is setSunil V L2-1/+7
2024-12-20hw/riscv: add riscv-iommu-sys platform deviceTomasz Jeznach1-0/+4
2024-10-31hw/riscv: add RISC-V IOMMU base emulationTomasz Jeznach1-0/+36
2024-10-30target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBITANG Tiancheng2-1/+32
2024-10-02hw/riscv: Respect firmware ELF entry pointSamuel Holland1-2/+2
2024-06-26hw/riscv/virt.c: add address-cells in create_fdt_one_aplic()Daniel Henrique Barboza1-0/+1
2024-02-21hw/riscv/virt.h: correct typosManos Pitsidianakis1-2/+2
2024-01-10hw/riscv/virt: Update GPEX MMIO related propertiesSunil V L1-0/+1
2024-01-10hw/riscv: virt: Make few IMSIC macros and functions publicSunil V L1-0/+25
2023-09-08riscv: spelling fixesMichael Tokarev1-1/+1
2023-07-10hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.Tommy Wu1-3/+6
2023-06-13hw/riscv/opentitan: Correct OpenTitanState parent type/sizePhilippe Mathieu-Daudé1-1/+2
2023-06-13hw/riscv/opentitan: Explicit machine type definitionPhilippe Mathieu-Daudé1-1/+2
2023-06-13hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definitionPhilippe Mathieu-Daudé1-0/+2
2023-03-06hw/riscv/virt: Enable basic ACPI infrastructureSunil V L1-0/+1
2023-03-06hw/riscv/virt: Add memmap pointer to RiscVVirtStateSunil V L1-0/+1
2023-03-06hw/riscv/virt: Add a switch to disable ACPISunil V L1-0/+2
2023-03-06hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fieldsSunil V L1-0/+2
2023-03-01hw/riscv: Move the dtb load bits outside of create_fdt()Bin Meng1-0/+1
2023-02-16hw/riscv/boot.c: make riscv_load_initrd() staticDaniel Henrique Barboza1-1/+0
2023-02-16hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza1-0/+1
2023-02-16hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza1-0/+1
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza1-1/+1
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza1-1/+3
2023-02-07include/hw/riscv/opentitan: update opentitan IRQsWilfred Mallawa1-7/+7
2023-01-20hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()Daniel Henrique Barboza1-2/+2
2023-01-20hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()Daniel Henrique Barboza1-3/+3
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza1-1/+1
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza1-2/+1
2023-01-20hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza1-2/+2
2023-01-20hw/riscv/sifive_u: use 'fdt' from MachineStateDaniel Henrique Barboza1-3/+0
2023-01-20hw/riscv/spike: use 'fdt' from MachineStateDaniel Henrique Barboza1-2/+0
2023-01-20hw/riscv/boot.c: Introduce riscv_find_firmware()Bin Meng1-0/+2
2023-01-20hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza1-0/+1
2023-01-20hw/riscv/boot.c: make riscv_find_firmware() staticDaniel Henrique Barboza1-1/+0
2023-01-08include: Include headers where neededMarkus Armbruster6-2/+10
2023-01-06hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng5-5/+5
2023-01-06hw/riscv: virt: Fix the value of "riscv, ndev" in the dtbBin Meng1-3/+2
2023-01-06hw/riscv: sifive_e: Fix the number of interrupt sources of PLICBin Meng1-1/+6
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