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| author | Bin Meng <bin.meng@windriver.com> | 2020-07-19 23:49:08 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-08-21 22:37:55 -0700 |
| commit | 6eaf9cf56f0f6e3faf73273f93cfe3e2e9fd0786 (patch) | |
| tree | 7d6cd382e30b252392db16e2ce1ba9fd60e51b50 /include/hw/riscv | |
| parent | ec80f8745931f0c8f8f2251e16bcc69170cf6f27 (diff) | |
| download | qemu-6eaf9cf56f0f6e3faf73273f93cfe3e2e9fd0786.zip qemu-6eaf9cf56f0f6e3faf73273f93cfe3e2e9fd0786.tar.gz qemu-6eaf9cf56f0f6e3faf73273f93cfe3e2e9fd0786.tar.bz2 | |
hw/riscv: sifive_u: Add a dummy L2 cache controller device
It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index aba4d01..d3c0c00 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -71,6 +71,7 @@ enum { SIFIVE_U_DEBUG, SIFIVE_U_MROM, SIFIVE_U_CLINT, + SIFIVE_U_L2CC, SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, @@ -86,6 +87,9 @@ enum { }; enum { + SIFIVE_U_L2CC_IRQ0 = 1, + SIFIVE_U_L2CC_IRQ1 = 2, + SIFIVE_U_L2CC_IRQ2 = 3, SIFIVE_U_UART0_IRQ = 4, SIFIVE_U_UART1_IRQ = 5, SIFIVE_U_GPIO_IRQ0 = 7, |