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| author | Wilfred Mallawa <wilfred.mallawa@wdc.com> | 2023-01-23 16:36:21 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:22 +1000 |
| commit | 7ae714628745e28e0f1e2d5ad0f95b27a40ff5c2 (patch) | |
| tree | 90e1cada7358b47a1c222f4618c5d962fd73c587 /include/hw/riscv | |
| parent | 3de1fb712a072992d72bc99c2b70978132ee44d0 (diff) | |
| download | qemu-7ae714628745e28e0f1e2d5ad0f95b27a40ff5c2.zip qemu-7ae714628745e28e0f1e2d5ad0f95b27a40ff5c2.tar.gz qemu-7ae714628745e28e0f1e2d5ad0f95b27a40ff5c2.tar.bz2 | |
include/hw/riscv/opentitan: update opentitan IRQs
Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.
OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
Memory layout as per [1]
[1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/opentitan.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 7659d1b..c40b050 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -94,9 +94,9 @@ enum { IBEX_DEV_EDNO, IBEX_DEV_EDN1, IBEX_DEV_ALERT_HANDLER, - IBEX_DEV_NMI_GEN, + IBEX_DEV_SRAM_CTRL, IBEX_DEV_OTBN, - IBEX_DEV_PERI, + IBEX_DEV_IBEX_CFG, }; enum { @@ -108,11 +108,11 @@ enum { IBEX_UART0_RX_BREAK_ERR_IRQ = 6, IBEX_UART0_RX_TIMEOUT_IRQ = 7, IBEX_UART0_RX_PARITY_ERR_IRQ = 8, - IBEX_TIMER_TIMEREXPIRED0_0 = 127, - IBEX_SPI_HOST0_ERR_IRQ = 134, - IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135, - IBEX_SPI_HOST1_ERR_IRQ = 136, - IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137, + IBEX_TIMER_TIMEREXPIRED0_0 = 124, + IBEX_SPI_HOST0_ERR_IRQ = 131, + IBEX_SPI_HOST0_SPI_EVENT_IRQ = 132, + IBEX_SPI_HOST1_ERR_IRQ = 133, + IBEX_SPI_HOST1_SPI_EVENT_IRQ = 134, }; #endif |