index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
hw
/
riscv
Age
Commit message (
Expand
)
Author
Files
Lines
2021-01-16
riscv: Pass RISCVHartArrayState by pointer
Alistair Francis
4
-19
/
+17
2021-01-16
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
Bin Meng
1
-5
/
+1
2021-01-16
RISC-V: Place DTB at 3GB boundary instead of 4GB
Atish Patra
1
-4
/
+4
2020-12-17
riscv/opentitan: Update the OpenTitan memory layout
Alistair Francis
1
-24
/
+57
2020-12-17
hw/riscv: Use the CPU to determine if 32-bit
Alistair Francis
4
-34
/
+24
2020-12-17
hw/riscv: sifive_u: Remove compile time XLEN checks
Alistair Francis
1
-25
/
+30
2020-12-17
hw/riscv: spike: Remove compile time XLEN checks
Alistair Francis
1
-21
/
+24
2020-12-17
hw/riscv: virt: Remove compile time XLEN checks
Alistair Francis
1
-15
/
+17
2020-12-17
hw/riscv: boot: Remove compile time XLEN checks
Alistair Francis
4
-28
/
+34
2020-12-17
riscv: virt: Remove target macro conditionals
Alistair Francis
1
-1
/
+1
2020-12-17
riscv: spike: Remove target macro conditionals
Alistair Francis
1
-1
/
+1
2020-12-17
hw/riscv: Expand the is 32-bit check to support more CPUs
Alistair Francis
1
-1
/
+11
2020-12-17
hw/riscv: microchip_pfsoc: add QSPI NOR flash
Vitaly Wool
1
-0
/
+21
2020-12-17
hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
Anup Patel
1
-0
/
+15
2020-12-15
vl: make qemu_get_machine_opts static
Paolo Bonzini
2
-8
/
+4
2020-12-10
vl: extract softmmu/datadir.c
Paolo Bonzini
1
-0
/
+1
2020-12-10
riscv: do not use ram_size global
Paolo Bonzini
1
-2
/
+3
2020-11-03
hw/riscv: microchip_pfsoc: Hook the I2C1 controller
Bin Meng
1
-0
/
+6
2020-11-03
hw/riscv: microchip_pfsoc: Correct DDR memory map
Bin Meng
1
-6
/
+44
2020-11-03
hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
Bin Meng
1
-1
/
+10
2020-11-03
hw/riscv: microchip_pfsoc: Connect the SYSREG module
Bin Meng
2
-3
/
+7
2020-11-03
hw/riscv: microchip_pfsoc: Connect the IOSCB module
Bin Meng
2
-5
/
+9
2020-11-03
hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
Bin Meng
2
-0
/
+19
2020-11-03
hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps
Bin Meng
1
-0
/
+18
2020-11-03
hw/riscv: virt: Allow passing custom DTB
Anup Patel
1
-7
/
+20
2020-11-03
hw/riscv: sifive_u: Allow passing custom DTB
Anup Patel
1
-8
/
+20
2020-10-22
hw/riscv: Load the kernel after the firmware
Alistair Francis
6
-15
/
+42
2020-10-22
hw/riscv: Add a riscv_is_32_bit() function
Alistair Francis
1
-0
/
+9
2020-10-22
hw/riscv: Return the end address of the loaded firmware
Alistair Francis
1
-11
/
+17
2020-10-22
hw/riscv: sifive_u: Allow specifying the CPU
Alistair Francis
1
-5
/
+13
2020-09-25
load_elf: Remove unused address variables from callers
BALATON Zoltan
1
-4
/
+4
2020-09-22
sifive_u: Register "start-in-flash" as class property
Eduardo Habkost
1
-8
/
+8
2020-09-22
sifive_e: Register "revb" as class property
Eduardo Habkost
1
-5
/
+6
2020-09-18
sifive_u: Rename memmap enum constants
Eduardo Habkost
1
-78
/
+78
2020-09-18
sifive_e: Rename memmap enum constants
Eduardo Habkost
1
-41
/
+41
2020-09-09
hw/riscv: Sort the Kconfig options in alphabetical order
Bin Meng
1
-29
/
+29
2020-09-09
hw/riscv: Drop CONFIG_SIFIVE
Bin Meng
1
-9
/
+5
2020-09-09
hw/riscv: Always build riscv_hart.c
Bin Meng
2
-10
/
+1
2020-09-09
hw/riscv: Move sifive_test model to hw/misc
Bin Meng
4
-102
/
+2
2020-09-09
hw/riscv: Move sifive_uart model to hw/char
Bin Meng
5
-197
/
+4
2020-09-09
hw/riscv: Move riscv_htif model to hw/char
Bin Meng
4
-266
/
+1
2020-09-09
hw/riscv: Move sifive_plic model to hw/intc
Bin Meng
7
-529
/
+9
2020-09-09
hw/riscv: Move sifive_clint model to hw/intc
Bin Meng
8
-272
/
+10
2020-09-09
hw/riscv: Move sifive_gpio model to hw/gpio
Bin Meng
5
-406
/
+2
2020-09-09
hw/riscv: Move sifive_u_otp model to hw/misc
Bin Meng
3
-192
/
+1
2020-09-09
hw/riscv: Move sifive_u_prci model to hw/misc
Bin Meng
3
-170
/
+1
2020-09-09
hw/riscv: Move sifive_e_prci model to hw/misc
Bin Meng
4
-127
/
+2
2020-09-09
hw/riscv: sifive_u: Connect a DMA controller
Bin Meng
2
-0
/
+31
2020-09-09
hw/riscv: clint: Avoid using hard-coded timebase frequency
Bin Meng
6
-16
/
+28
2020-09-09
hw/riscv: microchip_pfsoc: Hook GPIO controllers
Bin Meng
1
-0
/
+14
[next]