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authorAnup Patel <anup.patel@wdc.com>2020-11-11 15:17:25 +0530
committerAlistair Francis <alistair.francis@wdc.com>2020-12-17 21:56:43 -0800
commit10b43754cf299af85bdb1996594ddd54bc517094 (patch)
treea482992e51c545eac99b57d8399a14bc71c03edf /hw/riscv
parent75ee62ac606bfc9eb59310b9446df3434bf6e8c2 (diff)
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hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
The sifive_u machine emulates two UARTs but we have only UART0 DT node in the generated DTB so this patch adds UART1 DT node in the generated DTB. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201111094725.3768755-1-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
-rw-r--r--hw/riscv/sifive_u.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e7f6dc5..a629416 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -386,6 +386,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/soc/serial@%lx",
+ (long)memmap[SIFIVE_U_DEV_UART1].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_DEV_UART1].base,
+ 0x0, memmap[SIFIVE_U_DEV_UART1].size);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
+
+ qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/serial@%lx",
(long)memmap[SIFIVE_U_DEV_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");