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2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis1-24/+57
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis4-34/+24
2020-12-17hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis1-25/+30
2020-12-17hw/riscv: spike: Remove compile time XLEN checksAlistair Francis1-21/+24
2020-12-17hw/riscv: virt: Remove compile time XLEN checksAlistair Francis1-15/+17
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis4-28/+34
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis1-1/+1
2020-12-17riscv: spike: Remove target macro conditionalsAlistair Francis1-1/+1
2020-12-17hw/riscv: Expand the is 32-bit check to support more CPUsAlistair Francis1-1/+11
2020-12-17hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool1-0/+21
2020-12-17hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel1-0/+15
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini2-8/+4
2020-12-10vl: extract softmmu/datadir.cPaolo Bonzini1-0/+1
2020-12-10riscv: do not use ram_size globalPaolo Bonzini1-2/+3
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng1-0/+6
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng1-6/+44
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng1-1/+10
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2-3/+7
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2-5/+9
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2-0/+19
2020-11-03hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng1-0/+18
2020-11-03hw/riscv: virt: Allow passing custom DTBAnup Patel1-7/+20
2020-11-03hw/riscv: sifive_u: Allow passing custom DTBAnup Patel1-8/+20
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis6-15/+42
2020-10-22hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis1-0/+9
2020-10-22hw/riscv: Return the end address of the loaded firmwareAlistair Francis1-11/+17
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis1-5/+13
2020-09-25load_elf: Remove unused address variables from callersBALATON Zoltan1-4/+4
2020-09-22sifive_u: Register "start-in-flash" as class propertyEduardo Habkost1-8/+8
2020-09-22sifive_e: Register "revb" as class propertyEduardo Habkost1-5/+6
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost1-78/+78
2020-09-18sifive_e: Rename memmap enum constantsEduardo Habkost1-41/+41
2020-09-09hw/riscv: Sort the Kconfig options in alphabetical orderBin Meng1-29/+29
2020-09-09hw/riscv: Drop CONFIG_SIFIVEBin Meng1-9/+5
2020-09-09hw/riscv: Always build riscv_hart.cBin Meng2-10/+1
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng4-102/+2
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng5-197/+4
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng4-266/+1
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng7-529/+9
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng8-272/+10
2020-09-09hw/riscv: Move sifive_gpio model to hw/gpioBin Meng5-406/+2
2020-09-09hw/riscv: Move sifive_u_otp model to hw/miscBin Meng3-192/+1
2020-09-09hw/riscv: Move sifive_u_prci model to hw/miscBin Meng3-170/+1
2020-09-09hw/riscv: Move sifive_e_prci model to hw/miscBin Meng4-127/+2
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng2-0/+31
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng6-16/+28
2020-09-09hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng1-0/+14
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng1-0/+39
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2-0/+16
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2-0/+24
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