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AgeCommit message (Expand)AuthorFilesLines
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa1-3/+9
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel1-0/+10
2022-03-03hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel2-81/+359
2022-03-03hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel2-53/+239
2022-02-16hw/riscv: virt: Use AIA INTC compatible string when availableAnup Patel1-2/+11
2022-01-21hw/riscv: Remove macros for ELF BIOS image namesAnup Patel1-2/+2
2022-01-21hw/riscv: spike: Allow using binary firmware as biosAnup Patel1-16/+25
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang2-26/+73
2022-01-21riscv: opentitan: fixup plic stride lenWilfred Mallawa1-1/+1
2022-01-08hw/riscv: Use error_fatal for SoC realisationAlistair Francis4-4/+4
2021-12-20hw/riscv: Use load address rather than entry point for fw_dynamic next_addrJessica Clarke1-3/+10
2021-12-15hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster2-2/+2
2021-12-15hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster1-1/+12
2021-10-28hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis1-2/+2
2021-10-28hw/riscv: virt: Use the PLIC config helper functionAlistair Francis1-19/+1
2021-10-28hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis1-13/+1
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis1-13/+1
2021-10-28hw/riscv: boot: Add a PLIC config string functionAlistair Francis1-0/+25
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis1-1/+1
2021-10-22hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
2021-10-22hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
2021-10-22hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...Bin Meng1-16/+20
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis1-5/+17
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-1/+1
2021-10-22hw/riscv: virt: Use machine->ram as the system memoryMingwang Li1-4/+2
2021-10-07hw/riscv: shakti_c: Mark as not user creatableAlistair Francis1-0/+7
2021-09-21hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis1-1/+1
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel1-1/+112
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel1-200/+327
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel6-24/+44
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel7-12/+12
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis2-1/+55
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis1-0/+3
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis5-5/+6
2021-09-21hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-0/+8
2021-09-01hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell1-13/+20
2021-09-01hw/riscv: virt: Move flash node to rootBin Meng1-1/+1
2021-09-01hw/char: Add config for shakti uartVijai Kumar K1-4/+1
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell4-4/+0
2021-07-20hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machinesPhilippe Mathieu-Daudé2-1/+6
2021-07-15hw/riscv/boot: Check the error of fdt_pack()Alistair Francis1-2/+4
2021-07-15hw/riscv: opentitan: Add the flash aliasAlistair Francis1-0/+6
2021-07-15hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis1-0/+3
2021-07-15hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng1-2/+3
2021-07-15hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng1-2/+5
2021-06-24hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis1-3/+11
2021-06-08hw/riscv: microchip_pfsoc: Support direct kernel bootBin Meng1-3/+78
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