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| author | Anup Patel <anup.patel@wdc.com> | 2022-02-20 14:25:26 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-03-03 13:14:50 +1000 |
| commit | 0631aaae31cccf5ae61e8c67c198e064bfaafc66 (patch) | |
| tree | ec2a60aac36861b8aa015c4e68bfdeb7803e4f3d /hw/riscv | |
| parent | c65bc383edc7aa7c12afcdad3be30521b3280203 (diff) | |
| download | qemu-0631aaae31cccf5ae61e8c67c198e064bfaafc66.zip qemu-0631aaae31cccf5ae61e8c67c198e064bfaafc66.tar.gz qemu-0631aaae31cccf5ae61e8c67c198e064bfaafc66.tar.bz2 | |
hw/riscv: virt: Increase maximum number of allowed CPUs
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220220085526.808674-6-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/virt.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94fbf63..da50cbe 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -45,6 +45,16 @@ #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" +/* + * The virt machine physical address space used by some of the devices + * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, + * number of CPUs, and number of IMSIC guest files. + * + * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, + * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization + * of virt machine physical address space. + */ + #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) #if VIRT_IMSIC_GROUP_MAX_SIZE < \ IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) |