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AgeCommit message (Expand)AuthorFilesLines
2021-09-21hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis1-1/+1
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel1-1/+112
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel1-200/+327
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel6-24/+44
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel7-12/+12
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis2-1/+55
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis1-0/+3
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis5-5/+6
2021-09-21hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-0/+8
2021-09-01hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell1-13/+20
2021-09-01hw/riscv: virt: Move flash node to rootBin Meng1-1/+1
2021-09-01hw/char: Add config for shakti uartVijai Kumar K1-4/+1
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell4-4/+0
2021-07-20hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machinesPhilippe Mathieu-Daudé2-1/+6
2021-07-15hw/riscv/boot: Check the error of fdt_pack()Alistair Francis1-2/+4
2021-07-15hw/riscv: opentitan: Add the flash aliasAlistair Francis1-0/+6
2021-07-15hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis1-0/+3
2021-07-15hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng1-2/+3
2021-07-15hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng1-2/+5
2021-06-24hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis1-3/+11
2021-06-08hw/riscv: microchip_pfsoc: Support direct kernel bootBin Meng1-3/+78
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng3-12/+6
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng2-2/+10
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng3-3/+15
2021-06-08hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng1-2/+5
2021-06-08hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng1-3/+3
2021-05-11hw/riscv: Fix OT IBEX reset vectorAlexander Wagner1-1/+1
2021-05-11hw/riscv: Enable VIRTIO_VGA for RISC-V virt machineAlistair Francis1-0/+1
2021-05-11hw/opentitan: Update the interrupt layoutAlistair Francis1-4/+4
2021-05-11hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K1-0/+8
2021-05-11riscv: Add initial support for Shakti C machineVijai Kumar K3-0/+184
2021-05-11hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]Bin Meng1-1/+1
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth2-2/+0
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth6-6/+0
2021-05-02hw: Do not include hw/irq.h if it is not necessaryThomas Huth1-1/+0
2021-03-22hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng1-0/+6
2021-03-22hw/riscv: allow ramfb on virtAsherah Connor1-0/+3
2021-03-22hw/riscv: Add fw_cfg support to virtAsherah Connor2-0/+31
2021-03-11Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-docs-xen-upda...Peter Maydell1-10/+10
2021-03-10hw/riscv: migrate fdt field to generic MachineStateAlex Bennée1-10/+10
2021-03-09qtest: delete superfluous inclusions of qtest.hChen Qun1-1/+0
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng1-2/+33
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng1-0/+10
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng1-7/+7
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng6-37/+19
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2-2/+42
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2-0/+54
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis4-19/+17
2021-01-16hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng1-5/+1
2021-01-16RISC-V: Place DTB at 3GB boundary instead of 4GBAtish Patra1-4/+4
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