aboutsummaryrefslogtreecommitdiff
path: root/hw/pci-bridge
AgeCommit message (Expand)AuthorFilesLines
2024-04-25Merge tag 'hw-misc-20240425' of https://github.com/philmd/qemu into stagingRichard Henderson1-2/+1
2024-04-25hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return booleanZhao Liu1-2/+1
2024-04-25hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell2-3/+3
2024-03-13Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ...Peter Maydell1-1/+1
2024-03-12hw/pci-bridge/cxl_upstream: Fix missing ERRP_GUARD() in cxl_usp_realize()Zhao Liu1-0/+1
2024-03-12hw/pci-bridge/pxb-cxl: Drop RAS capability from host bridge.Jonathan Cameron1-1/+1
2024-03-12bulk: Access existing variables initialized to &S->F when availablePhilippe Mathieu-Daudé1-1/+1
2024-03-12hw/pci-bridge/cxl_upstream: Fix missing ERRP_GUARD() in cxl_usp_realize()Zhao Liu1-0/+1
2024-03-09hw/pci-bridge/cxl_upstream: Fix problem with g_steal_pointer()Thomas Huth1-4/+4
2024-02-14hw/cxl: Standardize all references on CXL r3.1 and minor updatesJonathan Cameron3-6/+6
2024-02-14hw/pci-bridge/cxl_upstream: Drop g_malloc() failure handlingJonathan Cameron1-6/+0
2024-01-04Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell1-2/+0
2023-12-31meson: remove CONFIG_ALLPaolo Bonzini1-2/+0
2023-12-30hw/pci-bridge: Constify VMStateRichard Henderson7-7/+7
2023-11-07hw/pci-bridge/cxl_downstream: Set default link width and link speedJonathan Cameron1-0/+14
2023-11-07hw/cxl/mbox: Add Physical Switch Identify command.Jonathan Cameron1-3/+1
2023-11-07hw/pci-bridge/cxl_upstream: Move defintion of device to header.Jonathan Cameron1-10/+1
2023-11-07hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExtJonathan Cameron3-3/+3
2023-10-04hw/pci-bridge/cxl-upstream: Add serial number extended capability supportJonathan Cameron1-2/+13
2023-09-21hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBISDave Jiang1-1/+1
2023-09-20hw/pci: spelling fixesMichael Tokarev2-2/+2
2023-08-03hw/pci-bridge/cxl_upstream.c: Use g_new0() in build_cdat_table()Peter Maydell1-4/+1
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé1-2/+2
2023-05-19hw/pci-bridge: make building pcie-to-pci bridge configurableSebastian Ott2-1/+7
2023-05-19hw/cxl: cdat: Fix failure to free buffer in erorr pathsJonathan Cameron1-0/+3
2023-04-24hw/pci-bridge: Make PCIe and CXL PXB Devices inherit from TYPE_PXB_DEVJonathan Cameron1-40/+19
2023-04-24hw/pci-bridge: pci_expander_bridge fix type in pxb_cxl_dev_reset()Jonathan Cameron1-1/+1
2023-03-07hw/pxb-cxl: Support passthrough HDM Decoders unless overriddenJonathan Cameron1-5/+39
2023-03-07hw/pci-bridge/cxl_root_port: Wire up MSIJonathan Cameron1-0/+61
2023-03-07hw/pci-bridge/cxl_root_port: Wire up AERJonathan Cameron1-0/+3
2023-03-02hw/pci-bridge/cxl_downstream: Fix type naming mismatchJonathan Cameron1-1/+1
2023-02-27hw: Move ich9.h to southbridge/Bernhard Beschow1-1/+1
2023-01-28pci: acpi hotplug: rename x-native-hotplug to x-do-not-expose-native-hotplug-capIgor Mammedov1-1/+6
2023-01-28pci_bridge: remove whitespaceIgor Mammedov1-1/+0
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé1-1/+1
2023-01-08include/hw/cxl: Move typedef PXBDev to cxl.h, and put it to useMarkus Armbruster1-1/+0
2023-01-08include/hw/pci: Break inclusion loop pci_bridge.h and cxl.hMarkus Armbruster1-1/+1
2022-12-21pci: drop redundant PCIDeviceClass::is_bridge fieldIgor Mammedov9-9/+0
2022-12-21remove DEC 21154 PCI bridgeIgor Mammedov3-175/+0
2022-12-16pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase resetPeter Maydell1-5/+9
2022-12-16pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase resetPeter Maydell1-3/+5
2022-11-07hw/pci-bridge/cxl-upstream: Add a CDAT table access DOEJonathan Cameron1-1/+194
2022-06-16pci-bridge/cxl_downstream: Add a CXL switch downstream portJonathan Cameron2-1/+250
2022-06-16pci-bridge/cxl_upstream: Add a CXL switch upstream portJonathan Cameron2-1/+217
2022-06-09pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.Jonathan Cameron3-13/+38
2022-06-09hw/cxl: Make the CXL fixed memory window setup a machine parameter.Jonathan Cameron1-1/+1
2022-05-13CXL/cxl_component: Add cxl_get_hb_cstate()Jonathan Cameron1-0/+7
2022-05-13acpi/cxl: Create the CEDT (9.14.1)Ben Widawsky1-17/+0
2022-05-13hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)Ben Widawsky1-7/+59
2022-05-13hw/cxl/rp: Add a root portBen Widawsky4-1/+247
generated by cgit v1.1 at 2024-11-05 12:22:42 +0000