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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2023-10-23 17:07:54 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-11-07 03:39:11 -0500 |
| commit | 2710d49a7c8b9b117a46847c7ace5eb21d48e882 (patch) | |
| tree | 78667bd8e577eca9122e7c7237f1f9d1146d34b2 /hw/pci-bridge | |
| parent | c9460561edbd8b2d4adbf1f7c5cb4ad4d210de4c (diff) | |
| download | qemu-2710d49a7c8b9b117a46847c7ace5eb21d48e882.zip qemu-2710d49a7c8b9b117a46847c7ace5eb21d48e882.tar.gz qemu-2710d49a7c8b9b117a46847c7ace5eb21d48e882.tar.bz2 | |
hw/pci-bridge/cxl_upstream: Move defintion of device to header.
To avoid repetition of switch upstream port specific data in the
CXLDeviceState structure it will be necessary to access the switch USP
specific data from mailbox callbacks. Hence move it to cxl_device.h so it
is no longer an opaque structure.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Message-Id: <20231023160806.13206-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci-bridge')
| -rw-r--r-- | hw/pci-bridge/cxl_upstream.c | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index b81bb5f..3673718 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -14,6 +14,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" +#include "hw/pci-bridge/cxl_upstream_port.h" /* * Null value of all Fs suggested by IEEE RA guidelines for use of * EU, OUI and CID @@ -30,16 +31,6 @@ #define CXL_UPSTREAM_PORT_DVSEC_OFFSET \ (CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF) -typedef struct CXLUpstreamPort { - /*< private >*/ - PCIEPort parent_obj; - - /*< public >*/ - CXLComponentState cxl_cstate; - DOECap doe_cdat; - uint64_t sn; -} CXLUpstreamPort; - CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp) { return &usp->cxl_cstate; |