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| author | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-14 14:27:04 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-09-20 07:54:34 +0300 |
| commit | f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4 (patch) | |
| tree | db97cf9d628a18c15a28e0af6f92a818dbd80ef0 /hw/pci-bridge | |
| parent | 2431f4f184339f679ff665c75e927fc24f7bd430 (diff) | |
| download | qemu-f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4.zip qemu-f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4.tar.gz qemu-f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4.tar.bz2 | |
hw/pci: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/pci-bridge')
| -rw-r--r-- | hw/pci-bridge/cxl_downstream.c | 2 | ||||
| -rw-r--r-- | hw/pci-bridge/pci_expander_bridge.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 54f5073..5a2b749 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -42,7 +42,7 @@ static void latch_registers(CXLDownstreamPort *dsp) CXL2_DOWNSTREAM_PORT); } -/* TODO: Look at sharing this code acorss all CXL port types */ +/* TODO: Look at sharing this code across all CXL port types */ static void cxl_dsp_dvsec_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len) { diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index 613857b..535889f 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -263,7 +263,7 @@ static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin) /* * First carry out normal swizzle to handle - * multple root ports on a pxb instance. + * multiple root ports on a pxb instance. */ pin = pci_swizzle_map_irq_fn(pci_dev, pin); |