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2023-11-06target/hppa: Implement HAVGRichard Henderson4-0/+22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSUBRichard Henderson4-0/+53
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HADDRichard Henderson4-1/+79
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64Richard Henderson1-4/+4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use tcg_temp_new_i64 not tcg_temp_newRichard Henderson1-80/+82
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Adjust vmstate_env for pa2.0 tlbRichard Henderson1-37/+58
Split out the tlb to a subsection so that it can be separately versioned -- the format is only partially following the architecture and is partially guided by the qemu implementation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove remaining TARGET_REGISTER_BITS redirectionsRichard Henderson1-33/+13
The conversions to/from i64 can be eliminated entirely, folding computation into adjacent operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove most of the TARGET_REGISTER_BITS redirectionsRichard Henderson1-505/+407
Remove all but those intended to change type to or from i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove TARGET_REGISTER_BITSRichard Henderson11-299/+135
Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06hw/hppa: Use uint32_t instead of target_uregRichard Henderson1-6/+6
The size of target_ureg is going to change. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement IDTLBT, IITLBTRichard Henderson4-13/+100
Rename the existing insert tlb helpers to emphasize that they are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement STDBYRichard Henderson4-5/+213
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOMRichard Henderson2-0/+8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement SHRPDRichard Henderson2-32/+73
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement EXTRDRichard Henderson2-13/+36
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement DEPD, DEPDIRichard Henderson2-30/+69
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement LDD, LDCD, LDDA, STD, STDARichard Henderson2-4/+15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode ADDB double-wordRichard Henderson1-0/+11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode CMPIB double-wordRichard Henderson2-3/+18
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for cmpb instructionsRichard Henderson2-6/+15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for bb instructionsRichard Henderson2-6/+4
Manipulate the shift count so that the bit to be tested is always placed at the MSB. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for sub instructionsRichard Henderson2-17/+17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for add instructionsRichard Henderson2-18/+19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for cmpclr instructionsRichard Henderson2-8/+9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for unit instructionsRichard Henderson2-20/+19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for logical instructionsRichard Henderson2-12/+13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove TARGET_HPPA64Richard Henderson5-29/+8
Allow both user-only and system mode to run pa2.0 cpus. Avoid creating a separate qemu-system-hppa64 binary; force the qemu-hppa binary to use TARGET_ABI32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Drop attempted gdbstub support for hppa64Richard Henderson1-19/+13
There is no support for hppa64 in gdb. Any attempt to provide the data for the larger hppa64 registers results in an error from gdb. Mask CR_SAR writes to the width of the register: 5 or 6 bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06linux-user/hppa: Fixes for TARGET_ABI32Richard Henderson1-3/+3
Avoid target_ulong and use abi_* types. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_unit_condRichard Henderson1-9/+11
Hoist the resolution of d up one level above do_unit_cond. All computations are logical, and are simplified by using a mask of the correct width, after which the result may be compared with zero. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_sed_condRichard Henderson1-11/+13
Hoist the resolution of d up one level above do_sed_cond. The MOVB comparison and the existing shift/extract/deposit are all 32-bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_log_condRichard Henderson1-10/+38
Hoist the resolution of d up one level above do_log_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_sub_condRichard Henderson1-26/+47
Hoist the resolution of d up one level above do_sub_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_condRichard Henderson1-28/+54
Hoist the resolution of d up one level above do_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: sar register allows only 5 bits on 32-bit CPUHelge Deller1-2/+2
The sar shift amount register is limited to 5 bits when running a 32-bit CPU. Strip off the remaining bits. The interesting part is, that this register allows to detect at runtime if a physical CPU is capable to execute PA2.0 (64-bit) instructions. Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06target/hppa: Mask inputs in copy_iaoq_entryRichard Henderson1-2/+14
Ensure that the destination is always a valid GVA offset. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use copy_iaoq_entry for link in do_ibranchRichard Henderson1-1/+1
We need to make sure the link is masked properly along the use_nullify_skip path. The other three settings of a link register already use this. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]Richard Henderson1-13/+22
This will be how we ensure that the IAOQ is always valid per PSW.W, therefore all stores to these two variables must be done with this function. Use third argument -1 if the destination is always dynamic, and fourth argument NULL if the destination is always static. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass DisasContext to copy_iaoq_entryRichard Henderson1-19/+20
Interface change only, no functional effect. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix hppa64 addressingRichard Henderson2-13/+16
In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0. In space_select, the bits that choose the space depend on PSW_W. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Adjust hppa_cpu_dump_state for hppa64Richard Henderson1-9/+19
Dump all 64 bits for pa2.0 and low 32 bits for pa1.x. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Handle absolute addresses for pa2.0Richard Henderson2-2/+44
With pa2.0, absolute addresses are not the same as physical addresses, and undergo a transformation based on PSW_W. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Update cpu_hppa_get/put_psw for hppa64Richard Henderson1-11/+52
With 64-bit registers, there are 16 carry bits in the PSW. Clear reserved bits based on cpu revision. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement hppa_cpu_class_by_nameRichard Henderson2-2/+10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement cpu_listRichard Henderson2-0/+29
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Make HPPA_BTLB_ENTRIES variableRichard Henderson4-33/+38
Depend on hppa_is_pa20. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Introduce TYPE_HPPA64_CPURichard Henderson4-15/+26
Prepare for the qemu binary supporting both pa10 and pa20 at the same time. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix extrw and depw with sar for hppa64Richard Henderson1-2/+5
These are 32-bit operations regardless of processor. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix bb_sar for hppa64Richard Henderson1-3/+13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix do_add, do_sub for hppa64Richard Henderson1-18/+32
Select the proper carry bit for input to the arithmetic and for output for the condition. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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