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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-17 16:39:47 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 18:49:33 -0800 |
| commit | 1e9ab9fbe06b6b343409029f5be2f184d6b69fde (patch) | |
| tree | 933e56977559405dbacaeb1ac3f68ebea94a638f | |
| parent | bdcccc17acb3f4cbf85cc81601edc1f87e76e088 (diff) | |
| download | qemu-1e9ab9fbe06b6b343409029f5be2f184d6b69fde.zip qemu-1e9ab9fbe06b6b343409029f5be2f184d6b69fde.tar.gz qemu-1e9ab9fbe06b6b343409029f5be2f184d6b69fde.tar.bz2 | |
target/hppa: Fix bb_sar for hppa64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/hppa/translate.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b0cd12a..ffa367b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3073,14 +3073,21 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) { TCGv_reg tmp, tcg_r; DisasCond cond; + bool d = false; nullify_over(ctx); tmp = tcg_temp_new(); tcg_r = load_gpr(ctx, a->r); - tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); + if (cond_need_ext(ctx, d)) { + /* Force shift into [32,63] */ + tcg_gen_ori_reg(tmp, cpu_sar, 32); + tcg_gen_shl_reg(tmp, tcg_r, tmp); + } else { + tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); + } - cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); + cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); return do_cbranch(ctx, a->disp, a->n, &cond); } @@ -3088,12 +3095,15 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) { TCGv_reg tmp, tcg_r; DisasCond cond; + bool d = false; + int p; nullify_over(ctx); tmp = tcg_temp_new(); tcg_r = load_gpr(ctx, a->r); - tcg_gen_shli_reg(tmp, tcg_r, a->p); + p = a->p | (cond_need_ext(ctx, d) ? 32 : 0); + tcg_gen_shli_reg(tmp, tcg_r, p); cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); return do_cbranch(ctx, a->disp, a->n, &cond); |