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author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-26 19:03:34 -0700 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 18:49:33 -0800 |
commit | f13bf343ccdb7df14233133f42670e1b16bb6b20 (patch) | |
tree | 6ed5a85ecab97a299a014f0b9f6b0de11832632a | |
parent | 9a91dd845277dd1d7c4c8f37662aa076e685dccc (diff) | |
download | qemu-f13bf343ccdb7df14233133f42670e1b16bb6b20.zip qemu-f13bf343ccdb7df14233133f42670e1b16bb6b20.tar.gz qemu-f13bf343ccdb7df14233133f42670e1b16bb6b20.tar.bz2 |
target/hppa: Mask inputs in copy_iaoq_entry
Ensure that the destination is always a valid GVA offset.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r-- | target/hppa/translate.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c2db278..cf05d8b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -720,10 +720,22 @@ static target_ureg gva_offset_mask(DisasContext *ctx) static void copy_iaoq_entry(DisasContext *ctx, TCGv_reg dest, target_ureg ival, TCGv_reg vval) { - if (unlikely(ival == -1)) { + target_ureg mask = gva_offset_mask(ctx); + + if (ival != -1) { + tcg_gen_movi_reg(dest, ival & mask); + return; + } + tcg_debug_assert(vval != NULL); + + /* + * We know that the IAOQ is already properly masked. + * This optimization is primarily for "iaoq_f = iaoq_b". + */ + if (vval == cpu_iaoq_f || vval == cpu_iaoq_b) { tcg_gen_mov_reg(dest, vval); } else { - tcg_gen_movi_reg(dest, ival); + tcg_gen_andi_reg(dest, vval, mask); } } |