diff options
| author | Helge Deller <deller@gmx.de> | 2023-10-16 14:43:18 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 18:49:33 -0800 |
| commit | f3618f59f3559eae69c34e0fe621685614b4350d (patch) | |
| tree | 31d98f6c9caf73a3a5057bc4d5c606d45f811006 | |
| parent | f13bf343ccdb7df14233133f42670e1b16bb6b20 (diff) | |
| download | qemu-f3618f59f3559eae69c34e0fe621685614b4350d.zip qemu-f3618f59f3559eae69c34e0fe621685614b4350d.tar.gz qemu-f3618f59f3559eae69c34e0fe621685614b4350d.tar.bz2 | |
target/hppa: sar register allows only 5 bits on 32-bit CPU
The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.
The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.
Signed-off-by: Helge Deller <deller@gmx.de>
| -rw-r--r-- | target/hppa/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cf05d8b..1694b98 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2176,7 +2176,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) if (ctl == CR_SAR) { reg = load_gpr(ctx, a->r); tmp = tcg_temp_new(); - tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); cond_free(&ctx->null_cond); @@ -2237,7 +2237,7 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) TCGv_reg tmp = tcg_temp_new(); tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); - tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); cond_free(&ctx->null_cond); |