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2022-02-09spapr/vof: Install rom and nvram binariesAlexey Kardashevskiy1-0/+2
This installs VOF-related binaries (the firmware and the preformatted NVRAM) as those were left out when the VOF was submitted initially. Fixes: fc8c745d5015 ("spapr: Implement Open Firmware client interface") Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20220208103751.1587902-1-aik@ozlabs.ru> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09docs: rstfy confidential guest documentationCornelia Huck6-56/+67
Also rstfy the documentation for AMD SEV, and link it. The documentation for PEF had been merged into the pseries doc, fix the reference. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220204161251.241877-1-cohuck@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Change VSX instructions behavior to fill with zerosVíctor Colombo2-14/+16
ISA v3.1 changed some VSX instructions behavior by changing what the other words/doubleword in the result should contain when the result is only one word/doubleword. e.g. xsmaxdp operates on doubleword 0 and saves the result also in doubleword 0. Before, the second doubleword result was undefined according to the ISA, but now it's stated that it should be zeroed. Even tough the result was undefined before, hardware implementing these instructions already filled these fields with 0s. Changing every ISA version in QEMU to this behavior makes the results match what happens in hardware. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220204181944.65063-1-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: books: Remove excp_model argument from ppc_excp_apply_ailFabiano Rosas1-12/+13
We don't really need to check for exception model while applying AIL. We can check the lpcr_mask for the presence of LPCR_AIL/LPCR_HAIL. This removes one more instance of passing the exception model ID around. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220207183036.1507882-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Assert if MSR bits differ from msr_mask during exceptionsFabiano Rosas1-58/+6
We currently abort QEMU during the dispatch of an interrupt if we try to set MSR_HV without having MSR_HVB in the msr_mask. I think we should verify this for all MSR bits. There is no reason to ever have a MSR bit set if the corresponding bit is not set in that CPU's msr_mask. Note that this is not about the emulated code setting reserved bits. We clear the new_msr when starting to dispatch an exception, so if we end up with bits not present in the msr_mask that is a QEMU programming error. I kept the HSRR verification for BookS because it is the only CPU family that has HSRRs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220207183036.1507882-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: powerpc_excp: Move common code to the caller functionFabiano Rosas1-48/+9
Make the cpu-specific powerpc_excp_* functions a bit simpler by moving the bounds check and logging to powerpc_excp. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220207183036.1507882-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Remove powerpc_excp_legacyFabiano Rosas1-474/+3
Now that all CPU families have their own separate exception dispatching code we can remove powerpc_excp_legacy. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220207183036.1507882-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: Set SRRs directly in exception codeFabiano Rosas1-11/+2
The 7xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: Software TLB cleanupFabiano Rosas1-20/+6
This code applies only to the 7xx CPUs, so we can remove the switch statement. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: System Reset cleanupFabiano Rosas1-16/+2
Thre is no HV support in the 7xx. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: System Call exception cleanupFabiano Rosas1-8/+13
Remove the BookE code and add a comment explaining why we need to keep hypercall support even though this CPU does not have a hypervisor mode. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: Program exception cleanupFabiano Rosas1-4/+0
There's no ESR in the 7xx. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: External interrupt cleanupFabiano Rosas1-37/+0
There is no MSR_HV in the 7xx so remove the LPES0 handling. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: Machine Check exception cleanupFabiano Rosas1-24/+0
There's no MSR_HV in the 7xx. Also remove 40x and BookE code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Simplify powerpc_excp_7xxFabiano Rosas1-176/+9
Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_DECR POWERPC_EXCP_DLTLB POWERPC_EXCP_DSI POWERPC_EXCP_DSTLB POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FPU POWERPC_EXCP_IABR POWERPC_EXCP_IFTLB POWERPC_EXCP_ISI POWERPC_EXCP_MCHECK POWERPC_EXCP_PERFM POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SMI POWERPC_EXCP_SYSCALL POWERPC_EXCP_THERM POWERPC_EXCP_TRACE Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Introduce powerpc_excp_7xxFabiano Rosas1-0/+469
Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs (740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Merge 7x5 and 7x0 exception model IDsFabiano Rosas3-13/+11
Since we've split the exception code by exception model, the exception model IDs are becoming less useful. These two can be merged. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: Set SRRs directly in exception codeFabiano Rosas1-11/+2
The 6xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-12-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: Software TLB exceptions cleanupFabiano Rosas1-20/+11
This code applies only to the 6xx CPUs, so we can remove the switch statement. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: System Reset interrupt cleanupFabiano Rosas1-16/+2
There is no HV support in the 6xx. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: System Call exception cleanupFabiano Rosas1-19/+2
There is no Hypervisor mode in the 6xx CPUs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: Program exception cleanupFabiano Rosas1-4/+0
There's no ESR in the 6xx CPUs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: External interrupt cleanupFabiano Rosas1-37/+0
There's no Hypervisor mode in the 6xx, so remove all LPES0 logic. Also remove BookE IRQ code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: Machine Check exception cleanupFabiano Rosas1-24/+0
There's no MSR_HV in the 6xx CPUs. Also remove the 40x and BookE code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: Critical exception cleanupFabiano Rosas1-15/+0
This only applies to the G2s, the other 6xx CPUs will not have this vector registered. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Simplify powerpc_excp_6xxFabiano Rosas1-154/+9
Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_CRITICAL POWERPC_EXCP_DABR POWERPC_EXCP_DECR POWERPC_EXCP_DLTLB POWERPC_EXCP_DSI POWERPC_EXCP_DSTLB POWERPC_EXCP_DTLB POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FPA POWERPC_EXCP_FPU POWERPC_EXCP_IABR POWERPC_EXCP_IFTLB POWERPC_EXCP_ISI POWERPC_EXCP_ITLB POWERPC_EXCP_MCHECK POWERPC_EXCP_MEXTBR POWERPC_EXCP_NMEXTBR POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SMI POWERPC_EXCP_SYSCALL POWERPC_EXCP_TRACE Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Introduce powerpc_excp_6xxFabiano Rosas1-0/+469
Introduce a new powerpc_excp function specific for PowerPC 6xx CPUs (603, 604, G2, MPC5xx, MCP8xx). This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Merge exception model IDs for 6xx CPUsFabiano Rosas3-18/+13
We don't need three separate exception model IDs for the 603, 604 and G2. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Remove PowerPC 601 CPUsCédric Le Goater22-1659/+13
The PowerPC 601 processor is the first generation of processors to implement the PowerPC architecture. It was designed as a bridge processor and also could execute most of the instructions of the previous POWER architecture. It was found on the first Macs and IBM RS/6000 workstations. There is not much interest in keeping the CPU model of this POWER-PowerPC bridge processor. We have the 603 and 604 CPU models of the 60x family which implement the complete PowerPC instruction set. Cc: "Hervé Poussineau" <hpoussin@reactos.org> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203142756.1302515-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Fix radix loggingCédric Le Goater1-6/+2
ppc_radix64_partition_scoped_xlate() logs the host page protection bits variable but it is uninitialized. The value is set later on in ppc_radix64_check_prot(). Remove the output. Fixes: Coverity CID 1468942 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20220203142145.1301749-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: System Reset exception cleanupFabiano Rosas1-16/+2
There is no MSR_HV in BookE, so remove all of the HV logic. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-12-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Watchdog Timer interruptFabiano Rosas1-9/+2
Remove the switch as this function applies to BookE only. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: System Call exception cleanupFabiano Rosas1-19/+2
QEMU does not support BookE as a hypervisor. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Alignment interrupt cleanupFabiano Rosas1-7/+0
BookE has no DSISR or DAR. The proper registers ESR and DEAR were already set at this point. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: External interrupt cleanupFabiano Rosas1-33/+0
There is no LPES0 in BookE and no MSR_HV. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Instruction storage exception cleanupFabiano Rosas1-1/+0
The SRR1 should be set to the MSR value. There are no diagnostic bits in the SRR1 for BookE. Note that this fixes a bug where MSR_GS would be set and Linux would go into KVM code when there's no KVM guest. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Data Storage exception cleanupFabiano Rosas1-1/+1
There is no DSISR or DAR in BookE. Change to ESR and DEAR. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Machine Check cleanupsFabiano Rosas1-23/+6
There's no MSR_HV in BookE. Also remove 40x code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Critical exception cleanupFabiano Rosas1-15/+2
Remove 40x and G2 code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Simplify powerpc_excp_bookeFabiano Rosas1-151/+14
Differences from the generic powerpc_excp code: - No MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - SPEU needs special handling; - Big endian only; - Both 64 and 32 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_APU POWERPC_EXCP_CRITICAL POWERPC_EXCP_DEBUG POWERPC_EXCP_DECR POWERPC_EXCP_DSI POWERPC_EXCP_DTLB POWERPC_EXCP_EFPDI POWERPC_EXCP_EFPRI POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FIT POWERPC_EXCP_FPU POWERPC_EXCP_ISI POWERPC_EXCP_ITLB POWERPC_EXCP_MCHECK POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SPEU POWERPC_EXCP_SYSCALL POWERPC_EXCP_WDT Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Introduce powerpc_excp_bookeFabiano Rosas1-0/+474
Introduce a new powerpc_excp function specific for BookE CPUs. This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Remove 440x4 CPUFabiano Rosas1-83/+0
This CPU was partially removed due to lack of support in 2017 by commit aef7796057 ("ppc: remove non implemented cpu models"). Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220128221611.1221715-1-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-08Merge remote-tracking branch ↵Peter Maydell42-614/+1302
'remotes/pmaydell/tags/pull-target-arm-20220208' into staging target-arm queue: * Fix handling of SVE ZCR_LEN when using VHE * xlnx-zynqmp: 'Or' the QSPI / QSPI DMA IRQs * Don't ever enable PSCI when booting guest in EL3 * Adhere to SMCCC 1.3 section 5.2 * highbank: Fix issues with booting SMP * midway: Fix issues booting at all * boot: Drop existing dtb /psci node rather than retaining it * versal-virt: Always call arm_load_kernel() * force flag recalculation when messing with DAIF * hw/timer/armv7m_systick: Update clock source before enabling timer * hw/arm/smmuv3: Fix device reset * hw/intc/arm_gicv3_its: refactorings and minor bug fixes * hw/sensor: Add lsm303dlhc magnetometer device # gpg: Signature made Tue 08 Feb 2022 11:39:15 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20220208: (39 commits) hw/sensor: Add lsm303dlhc magnetometer device hw/intc/arm_gicv3_its: Split error checks hw/intc/arm_gicv3_its: Don't allow intid 1023 in MAPI/MAPTI hw/intc/arm_gicv3_its: In MAPC with V=0, don't check rdbase field hw/intc/arm_gicv3_its: Drop TableDesc and CmdQDesc valid fields hw/intc/arm_gicv3_its: Make update_ite() use ITEntry hw/intc/arm_gicv3_its: Pass ITE values back from get_ite() via a struct hw/intc/arm_gicv3_its: Avoid nested ifs in get_ite() hw/intc/arm_gicv3_its: Fix address calculation in get_ite() and update_ite() hw/intc/arm_gicv3_its: Pass CTEntry to update_cte() hw/intc/arm_gicv3_its: Keep CTEs as a struct, not a raw uint64_t hw/intc/arm_gicv3_its: Pass DTEntry to update_dte() hw/intc/arm_gicv3_its: Keep DTEs as a struct, not a raw uint64_t hw/intc/arm_gicv3_its: Use address_space_map() to access command queue packets hw/arm/smmuv3: Fix device reset hw/timer/armv7m_systick: Update clock source before enabling timer arm: force flag recalculation when messing with DAIF hw/arm: versal-virt: Always call arm_load_kernel() hw/arm/boot: Drop existing dtb /psci node rather than retaining it hw/arm/boot: Drop nb_cpus field from arm_boot_info ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-08hw/sensor: Add lsm303dlhc magnetometer deviceKevin Townsend5-0/+710
This commit adds emulation of the magnetometer on the LSM303DLHC. It allows the magnetometer's X, Y and Z outputs to be set via the mag-x, mag-y and mag-z properties, as well as the 12-bit temperature output via the temperature property. Sensor can be enabled with 'CONFIG_LSM303DLHC_MAG=y'. Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org> Message-id: 20220130095032.35392-1-kevin.townsend@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-08hw/intc/arm_gicv3_its: Split error checksPeter Maydell1-21/+31
In most of the ITS command processing, we check different error possibilities one at a time and log them appropriately. In process_mapti() and process_mapd() we have code which checks multiple error cases at once, which means the logging is less specific than it could be. Split those cases up. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220201193207.2771604-14-peter.maydell@linaro.org
2022-02-08hw/intc/arm_gicv3_its: Don't allow intid 1023 in MAPI/MAPTIPeter Maydell1-2/+1
When handling MAPI/MAPTI, we allow the supplied interrupt ID to be either 1023 or something in the valid LPI range. This is a mistake: only a real valid LPI is allowed. (The general behaviour of the ITS is that most interrupt ID fields require a value in the LPI range; the exception is that fields specifying a doorbell value, which are all in GICv4 commands, allow also 1023 to mean "no doorbell".) Remove the condition that incorrectly allows 1023 here. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220201193207.2771604-13-peter.maydell@linaro.org
2022-02-08hw/intc/arm_gicv3_its: In MAPC with V=0, don't check rdbase fieldPeter Maydell1-12/+12
In the MAPC command, if V=0 this is a request to delete a collection table entry and the rdbase field of the command packet will not be used. In particular, the specification says that the "UNPREDICTABLE if rdbase is not valid" only applies for V=1. We were doing a check-and-log-guest-error on rdbase regardless of whether the V bit was set, and also (harmlessly but confusingly) storing the contents of the rdbase field into the updated collection table entry. Update the code so that if V=0 we don't check or use the rdbase field value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220201193207.2771604-12-peter.maydell@linaro.org
2022-02-08hw/intc/arm_gicv3_its: Drop TableDesc and CmdQDesc valid fieldsPeter Maydell2-19/+14
Currently we track in the TableDesc and CmdQDesc structs the state of the GITS_BASER<n> and GITS_CBASER Valid bits. However we aren't very consistent abut checking the valid field: we test it in update_cte() and update_dte(), but not anywhere else we look things up in tables. The GIC specification says that it is UNPREDICTABLE if a guest fails to set any of these Valid bits before enabling the ITS via GITS_CTLR.Enabled. So we can choose to handle Valid == 0 as equivalent to a zero-length table. This is in fact how we're already catching this case in most of the table-access paths: when Valid is 0 we leave the num_entries fields in TableDesc or CmdQDesc set to zero, and then the out-of-bounds check "index >= num_entries" that we have to do anyway before doing any of these table lookups will always be true, catching the no-valid-table case without any extra code. So we can remove the checks on the valid field from update_cte() and update_dte(): since these happen after the bounds check there was never any case when the test could fail. That means the valid fields would be entirely unused, so just remove them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220201193207.2771604-11-peter.maydell@linaro.org
2022-02-08hw/intc/arm_gicv3_its: Make update_ite() use ITEntryPeter Maydell1-30/+32
Make the update_ite() struct use the new ITEntry struct, so that callers don't need to assemble the in-memory ITE data themselves, and only get_ite() and update_ite() need to care about that in-memory layout. We can then drop the no-longer-used IteEntry struct definition. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220201193207.2771604-10-peter.maydell@linaro.org
2022-02-08hw/intc/arm_gicv3_its: Pass ITE values back from get_ite() via a structPeter Maydell1-47/+55
In get_ite() we currently return the caller some of the fields of an Interrupt Table Entry via a set of pointer arguments, and validate some of them internally (interrupt type and valid bit) to return a simple true/false 'valid' indication. Define a new ITEntry struct which has all the fields that the in-memory ITE has, and bring the get_ite() function in to line with get_dte() and get_cte(). This paves the way for handling virtual interrupts, which will want a different subset of the fields in the ITE. Handling them under the old "lots of pointer arguments" scheme would have meant a confusingly large set of arguments for this function. The new struct ITEntry is obviously confusably similar to the existing IteEntry struct, whose fields are the raw 12 bytes of the in-memory ITE. In the next commit we will make update_ite() use ITEntry instead of IteEntry, which will allow us to delete the IteEntry struct and remove the confusion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220201193207.2771604-9-peter.maydell@linaro.org
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