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| author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-02-09 09:08:56 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-02-09 09:08:56 +0100 |
| commit | c50eaed135216597cd75f71cec79ae28a7996c06 (patch) | |
| tree | a4d1adf0afceff902efa362d20f0e3f37b8a9097 | |
| parent | 8f8c7932d4be3fe4dc0fb9540c48132de7382cab (diff) | |
| download | qemu-c50eaed135216597cd75f71cec79ae28a7996c06.zip qemu-c50eaed135216597cd75f71cec79ae28a7996c06.tar.gz qemu-c50eaed135216597cd75f71cec79ae28a7996c06.tar.bz2 | |
target/ppc: 6xx: Set SRRs directly in exception code
The 6xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| -rw-r--r-- | target/ppc/excp_helper.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 8016835..7bdda6f 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -554,7 +554,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1; if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) { cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); @@ -573,10 +572,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) */ new_msr = env->msr & ((target_ulong)1 << MSR_ME); - /* target registers */ - srr0 = SPR_SRR0; - srr1 = SPR_SRR1; - /* * Hypervisor emulation assistance interrupt only exists on server * arch 2.05 server or later. @@ -727,10 +722,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " "no HV support\n", excp); } - if (srr0 == SPR_HSRR0) { - cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " - "no HV support\n", excp); - } } /* @@ -742,10 +733,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) } /* Save PC */ - env->spr[srr0] = env->nip; + env->spr[SPR_SRR0] = env->nip; /* Save MSR */ - env->spr[srr1] = msr; + env->spr[SPR_SRR1] = msr; powerpc_set_excp_state(cpu, vector, new_msr); } |