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authorFabiano Rosas <farosas@linux.ibm.com>2022-02-09 09:08:56 +0100
committerCédric Le Goater <clg@kaod.org>2022-02-09 09:08:56 +0100
commita53ce46537f7d6a8541ab91154a151f13601f102 (patch)
tree1e59c2f333733adb0e90711ad0aefcf2aba05f81
parent784f5a3403097a4427c91e7f62d257a3dbbf751e (diff)
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target/ppc: 7xx: External interrupt cleanup
There is no MSR_HV in the 7xx so remove the LPES0 handling. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
-rw-r--r--target/ppc/excp_helper.c37
1 files changed, 0 insertions, 37 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 4996b96..5e2c2aa 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -815,44 +815,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
- {
- bool lpes0;
-
- cs = CPU(cpu);
-
- /*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
- */
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
- }
-
- if (!lpes0) {
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- }
- if (env->mpic_proxy) {
- /* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
- }
break;
- }
case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */
/*