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| author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-02-09 09:08:55 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-02-09 09:08:55 +0100 |
| commit | 3189fa391702314b84edbf0edbf25a5c08ccad9e (patch) | |
| tree | 99bdf760aac9feb66742acb0655b91d9ef4e8fe8 | |
| parent | 9b12ff43d428805d79315521ff2d242e67bb47ce (diff) | |
| download | qemu-3189fa391702314b84edbf0edbf25a5c08ccad9e.zip qemu-3189fa391702314b84edbf0edbf25a5c08ccad9e.tar.gz qemu-3189fa391702314b84edbf0edbf25a5c08ccad9e.tar.bz2 | |
target/ppc: 6xx: External interrupt cleanup
There's no Hypervisor mode in the 6xx, so remove all LPES0 logic.
Also remove BookE IRQ code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| -rw-r--r-- | target/ppc/excp_helper.c | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 734170d..a008115 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -625,44 +625,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) msr |= env->error_code; break; case POWERPC_EXCP_EXTERNAL: /* External input */ - { - bool lpes0; - - cs = CPU(cpu); - - /* - * Exception targeting modifiers - * - * LPES0 is supported on POWER7/8/9 - * LPES1 is not supported (old iSeries mode) - * - * On anything else, we behave as if LPES0 is 1 - * (externals don't alter MSR:HV) - */ -#if defined(TARGET_PPC64) - if (excp_model == POWERPC_EXCP_POWER7 || - excp_model == POWERPC_EXCP_POWER8 || - excp_model == POWERPC_EXCP_POWER9 || - excp_model == POWERPC_EXCP_POWER10) { - lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); - } else -#endif /* defined(TARGET_PPC64) */ - { - lpes0 = true; - } - - if (!lpes0) { - new_msr |= (target_ulong)MSR_HVB; - new_msr |= env->msr & ((target_ulong)1 << MSR_RI); - srr0 = SPR_HSRR0; - srr1 = SPR_HSRR1; - } - if (env->mpic_proxy) { - /* IACK the IRQ on delivery */ - env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); - } break; - } case POWERPC_EXCP_ALIGN: /* Alignment exception */ /* Get rS/rD and rA from faulting opcode */ /* |