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| author | Matheus Ferst <matheus.ferst@eldorado.org.br> | 2022-03-02 06:51:37 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:37 +0100 |
| commit | 85085bbc63791ab6fa02441c53b86369d70e4f86 (patch) | |
| tree | 377b28e283d15112a5f22dad6bda353587bd907e /target | |
| parent | 946c3491c6d75b8acfe881a33fa5d6a83c4cf6c3 (diff) | |
| download | qemu-85085bbc63791ab6fa02441c53b86369d70e4f86.zip qemu-85085bbc63791ab6fa02441c53b86369d70e4f86.tar.gz qemu-85085bbc63791ab6fa02441c53b86369d70e4f86.tar.bz2 | |
target/ppc: implement vsraq
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-23-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/insn32.decode | 1 | ||||
| -rw-r--r-- | target/ppc/translate/vmx-impl.c.inc | 23 |
2 files changed, 18 insertions, 6 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 96ee730..7a9fc1d 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -485,6 +485,7 @@ VSRAB 000100 ..... ..... ..... 01100000100 @VX VSRAH 000100 ..... ..... ..... 01101000100 @VX VSRAW 000100 ..... ..... ..... 01110000100 @VX VSRAD 000100 ..... ..... ..... 01111000100 @VX +VSRAQ 000100 ..... ..... ..... 01100000101 @VX ## Vector Integer Arithmetic Instructions diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 8a1e64d..27ed87f 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -834,9 +834,10 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv); TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv); TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv); -static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right) +static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right, + bool alg) { - TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0); + TCGv_i64 hi, lo, t0, t1, n, zero = tcg_constant_i64(0); REQUIRE_VECTOR(ctx); @@ -844,6 +845,7 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right) hi = tcg_temp_new_i64(); lo = tcg_temp_new_i64(); t0 = tcg_temp_new_i64(); + t1 = tcg_const_i64(0); get_avr64(lo, a->vra, false); get_avr64(hi, a->vra, true); @@ -853,7 +855,10 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right) tcg_gen_andi_i64(t0, n, 64); if (right) { tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo); - tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, zero, hi); + if (alg) { + tcg_gen_sari_i64(t1, lo, 63); + } + tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, t1, hi); } else { tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi); tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo); @@ -861,7 +866,11 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right) tcg_gen_andi_i64(n, n, 0x3F); if (right) { - tcg_gen_shr_i64(t0, hi, n); + if (alg) { + tcg_gen_sar_i64(t0, hi, n); + } else { + tcg_gen_shr_i64(t0, hi, n); + } } else { tcg_gen_shl_i64(t0, lo, n); } @@ -886,13 +895,15 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right) tcg_temp_free_i64(hi); tcg_temp_free_i64(lo); tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); tcg_temp_free_i64(n); return true; } -TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false); -TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true); +TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false, false); +TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true, false); +TRANS_FLAGS2(ISA310, VSRAQ, do_vector_shift_quad, true, true); #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \ static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \ |