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| author | Matheus Ferst <matheus.ferst@eldorado.org.br> | 2022-03-02 06:51:37 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:37 +0100 |
| commit | 946c3491c6d75b8acfe881a33fa5d6a83c4cf6c3 (patch) | |
| tree | 73f13de0b4478ad42b31584f4e4e9b771ecfbf13 /target | |
| parent | 3e39edb688a39cbeabce2ceff6395ddbfe69661a (diff) | |
| download | qemu-946c3491c6d75b8acfe881a33fa5d6a83c4cf6c3.zip qemu-946c3491c6d75b8acfe881a33fa5d6a83c4cf6c3.tar.gz qemu-946c3491c6d75b8acfe881a33fa5d6a83c4cf6c3.tar.bz2 | |
target/ppc: implement vsrq
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-22-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/insn32.decode | 1 | ||||
| -rw-r--r-- | target/ppc/translate/vmx-impl.c.inc | 40 |
2 files changed, 31 insertions, 10 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 3799065..96ee730 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -479,6 +479,7 @@ VSRB 000100 ..... ..... ..... 01000000100 @VX VSRH 000100 ..... ..... ..... 01001000100 @VX VSRW 000100 ..... ..... ..... 01010000100 @VX VSRD 000100 ..... ..... ..... 11011000100 @VX +VSRQ 000100 ..... ..... ..... 01000000101 @VX VSRAB 000100 ..... ..... ..... 01100000100 @VX VSRAH 000100 ..... ..... ..... 01101000100 @VX diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 49c722e..8a1e64d 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -834,11 +834,10 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv); TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv); TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv); -static bool trans_VSLQ(DisasContext *ctx, arg_VX *a) +static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right) { TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0); - REQUIRE_INSNS_FLAGS2(ctx, ISA310); REQUIRE_VECTOR(ctx); n = tcg_temp_new_i64(); @@ -852,19 +851,37 @@ static bool trans_VSLQ(DisasContext *ctx, arg_VX *a) get_avr64(n, a->vrb, true); tcg_gen_andi_i64(t0, n, 64); - tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi); - tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo); + if (right) { + tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo); + tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, zero, hi); + } else { + tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi); + tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo); + } tcg_gen_andi_i64(n, n, 0x3F); - tcg_gen_shl_i64(t0, lo, n); - set_avr64(a->vrt, t0, false); + if (right) { + tcg_gen_shr_i64(t0, hi, n); + } else { + tcg_gen_shl_i64(t0, lo, n); + } + set_avr64(a->vrt, t0, right); - tcg_gen_shl_i64(hi, hi, n); + if (right) { + tcg_gen_shr_i64(lo, lo, n); + } else { + tcg_gen_shl_i64(hi, hi, n); + } tcg_gen_xori_i64(n, n, 63); - tcg_gen_shr_i64(lo, lo, n); - tcg_gen_shri_i64(lo, lo, 1); + if (right) { + tcg_gen_shl_i64(hi, hi, n); + tcg_gen_shli_i64(hi, hi, 1); + } else { + tcg_gen_shr_i64(lo, lo, n); + tcg_gen_shri_i64(lo, lo, 1); + } tcg_gen_or_i64(hi, hi, lo); - set_avr64(a->vrt, hi, true); + set_avr64(a->vrt, hi, !right); tcg_temp_free_i64(hi); tcg_temp_free_i64(lo); @@ -874,6 +891,9 @@ static bool trans_VSLQ(DisasContext *ctx, arg_VX *a) return true; } +TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false); +TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true); + #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \ static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \ TCGv_vec sat, TCGv_vec a, \ |