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| author | Aaron Lindsay <aaron@os.amperecomputing.com> | 2019-01-21 10:23:14 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-01-21 10:38:56 +0000 |
| commit | 327dd5108bb3b66bb5102b659e83a4348a005f5e (patch) | |
| tree | 51d578434609865e38c45e018c66c8ee9a7e697f /target | |
| parent | 4b8afa1f99c3575f6cfb26770f90e9fd7bc45468 (diff) | |
| download | qemu-327dd5108bb3b66bb5102b659e83a4348a005f5e.zip qemu-327dd5108bb3b66bb5102b659e83a4348a005f5e.tar.gz qemu-327dd5108bb3b66bb5102b659e83a4348a005f5e.tar.bz2 | |
target/arm: Implement PMOVSSET
Add an array for PMOVSSET so we only define it for v7ve+ platforms
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181211151945.29137-7-aaron@os.amperecomputing.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/helper.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 8635220..460ab713 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1342,6 +1342,13 @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, env->cp15.c9_pmovsr &= ~value; } +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &= pmu_counter_mask(env); + env->cp15.c9_pmovsr |= value; +} + static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1718,6 +1725,24 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo pmovsset_cp_reginfo[] = { + /* PMOVSSET is not implemented in v7 before v7ve */ + { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsset_write, + .raw_writefn = raw_write }, + { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsset_write, + .raw_writefn = raw_write }, + REGINFO_SENTINEL +}; + static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5360,6 +5385,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) !arm_feature(env, ARM_FEATURE_PMSA)) { define_arm_cp_regs(cpu, v7mp_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + define_arm_cp_regs(cpu, pmovsset_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle |