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| author | Aaron Lindsay <aaron@os.amperecomputing.com> | 2019-01-21 10:23:14 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-01-21 10:38:55 +0000 |
| commit | 4b8afa1f99c3575f6cfb26770f90e9fd7bc45468 (patch) | |
| tree | 42b1769b94bca51a91292a7126c795dd8ac3ae07 /target | |
| parent | 033614c47de78409ad3fb39bb7bd1483b71c6789 (diff) | |
| download | qemu-4b8afa1f99c3575f6cfb26770f90e9fd7bc45468.zip qemu-4b8afa1f99c3575f6cfb26770f90e9fd7bc45468.tar.gz qemu-4b8afa1f99c3575f6cfb26770f90e9fd7bc45468.tar.bz2 | |
target/arm: Allow AArch32 access for PMCCFILTR
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181211151945.29137-6-aaron@os.amperecomputing.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/helper.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 2535c7d..8635220 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -994,6 +994,10 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { PMXEVTYPER_M | PMXEVTYPER_MT | \ PMXEVTYPER_EVTCOUNT) +#define PMCCFILTR 0xf8000000 +#define PMCCFILTR_M PMXEVTYPER_M +#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) + static inline uint32_t pmu_num_counters(CPUARMState *env) { return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; @@ -1297,10 +1301,26 @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { pmccntr_op_start(env); - env->cp15.pmccfiltr_el0 = value & 0xfc000000; + env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; + pmccntr_op_finish(env); +} + +static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_op_start(env); + /* M is not accessible from AArch32 */ + env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | + (value & PMCCFILTR); pmccntr_op_finish(env); } +static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* M is not visible in AArch32 */ + return env->cp15.pmccfiltr_el0 & PMCCFILTR; +} + static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1545,6 +1565,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .readfn = pmccntr_read, .writefn = pmccntr_write, .raw_readfn = raw_read, .raw_writefn = raw_write, }, #endif + { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, + .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS | ARM_CP_IO, + .resetvalue = 0, }, { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, .writefn = pmccfiltr_write, .raw_writefn = raw_write, |