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authorBruno Larsen (billionai) <bruno.larsen@eldorado.org.br>2021-11-04 09:37:16 -0300
committerDavid Gibson <david@gibson.dropbear.id.au>2021-11-09 10:32:53 +1100
commit236a628599b2d1307b3f3d095e0c15d7b7524f83 (patch)
tree68a1cbe3c25f0b5240c01e21055f6de73151b77f /target
parentec10f73eb92c0f72891808e58d4d47932e39797b (diff)
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target/ppc: implemented XXSPLTIDP instruction
Implemented the instruction XXSPLTIDP using decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211104123719.323713-23-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
-rw-r--r--target/ppc/insn64.decode2
-rw-r--r--target/ppc/translate/vsx-impl.c.inc10
2 files changed, 12 insertions, 0 deletions
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index bd71f61..20aa2b4 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -169,6 +169,8 @@ PLXVP 000001 00 0--.-- .................. \
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+XXSPLTIDP 000001 01 0000 -- -- ................ \
+ 100000 ..... 0010 . ................ @8RR_D
XXSPLTIW 000001 01 0000 -- -- ................ \
100000 ..... 0011 . ................ @8RR_D
XXSPLTI32DX 000001 01 0000 -- -- ................ \
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 7116141..180d329 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1476,6 +1476,16 @@ static bool trans_XXSPLTIW(DisasContext *ctx, arg_8RR_D *a)
return true;
}
+static bool trans_XXSPLTIDP(DisasContext *ctx, arg_8RR_D *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_dup_imm(MO_64, vsr_full_offset(a->xt), 16, 16,
+ helper_todouble(a->si));
+ return true;
+}
+
static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
{
TCGv_i32 imm;