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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-02-07 12:55:28 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-07 12:55:28 +0000 |
| commit | 1dca0549557caf962dc12dc0c225a98a6f2d5fa7 (patch) | |
| tree | 31644ab1facf28b511d7e9d3f9c984fd2afffd77 /target | |
| parent | 713acc316ddca119fe168e72846f1d2dd0548430 (diff) | |
| parent | 68aa851aa21741ab0a3c019b641d6ce72f68b3d5 (diff) | |
| download | qemu-1dca0549557caf962dc12dc0c225a98a6f2d5fa7.zip qemu-1dca0549557caf962dc12dc0c225a98a6f2d5fa7.tar.gz qemu-1dca0549557caf962dc12dc0c225a98a6f2d5fa7.tar.bz2 | |
Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190206' into staging
Queued target/hppa patches
# gpg: Signature made Wed 06 Feb 2019 10:50:06 GMT
# gpg: using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-hppa-20190206:
target/hppa: fix PSW Q bit behaviour to match hardware
target/hppa: fix setting registers via gdb
target/hppa: use tb_cflags() to access tb->cflags
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/hppa/gdbstub.c | 2 | ||||
| -rw-r--r-- | target/hppa/op_helper.c | 14 | ||||
| -rw-r--r-- | target/hppa/translate.c | 2 |
3 files changed, 11 insertions, 7 deletions
diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index e2e9c4d..3157a69 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -266,7 +266,7 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) case 65 ... 127: { uint64_t *fr = &env->fr[(n - 64) / 2]; - *fr = deposit64(*fr, val, (n & 1 ? 0 : 32), 32); + *fr = deposit64(*fr, (n & 1 ? 0 : 32), 32, val); } break; default: diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 912e8d5..6bf478e 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -665,11 +665,15 @@ void HELPER(reset)(CPUHPPAState *env) target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) { target_ulong psw = env->psw; - /* ??? On second reading this condition simply seems - to be undefined rather than a diagnosed trap. */ - if (nsm & ~psw & PSW_Q) { - hppa_dynamic_excp(env, EXCP_ILL, GETPC()); - } + /* + * Setting the PSW Q bit to 1, if it was not already 1, is an + * undefined operation. + * + * However, HP-UX 10.20 does this with the SSM instruction. + * Tested this on HP9000/712 and HP9000/785/C3750 and both + * machines set the Q bit from 0 to 1 without an exception, + * so let this go without comment. + */ env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); return psw & PSW_SM; } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ce05d56..51bfd98 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2059,7 +2059,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, /* FIXME: Respect PSW_S bit. */ nullify_over(ctx); tmp = dest_gpr(ctx, rt); - if (ctx->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); gen_helper_read_interval_timer(tmp); gen_io_end(); |