From 84b41e658b02a6738b47cc4e03176f1b81d9e1d1 Mon Sep 17 00:00:00 2001 From: "Emilio G. Cota" Date: Wed, 14 Feb 2018 22:05:46 -0500 Subject: target/hppa: use tb_cflags() to access tb->cflags Signed-off-by: Emilio G. Cota Message-Id: <1518663946-2326-1-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ce05d56..51bfd98 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2059,7 +2059,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, /* FIXME: Respect PSW_S bit. */ nullify_over(ctx); tmp = dest_gpr(ctx, rt); - if (ctx->base.tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); gen_helper_read_interval_timer(tmp); gen_io_end(); -- cgit v1.1 From 5c41496dd780fed67eadd64c59fc2cf21717ecf0 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Mon, 28 Jan 2019 17:53:33 +0100 Subject: target/hppa: fix setting registers via gdb While doing 'set $pcoqh=0xf0000000' i triggered the assertion below. The argument order for deposit64() is wrong, and val needs to be moved to the end. Signed-off-by: Sven Schnelle Message-Id: <20190128165333.3814-1-svens@stackframe.org> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/hppa/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index e2e9c4d..3157a69 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -266,7 +266,7 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) case 65 ... 127: { uint64_t *fr = &env->fr[(n - 64) / 2]; - *fr = deposit64(*fr, val, (n & 1 ? 0 : 32), 32); + *fr = deposit64(*fr, (n & 1 ? 0 : 32), 32, val); } break; default: -- cgit v1.1 From 68aa851aa21741ab0a3c019b641d6ce72f68b3d5 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 29 Jan 2019 20:14:02 +0100 Subject: target/hppa: fix PSW Q bit behaviour to match hardware PA-RISC specification says: "Setting the PSW Q-bit, PSW{28}, to 1 with this instruction, if it was not already 1, is an undefined operation." However, at least HP-UX 10.20 sets the Q bit from 0 to 1 with the SSM instruction. Tested this both on HP9000/712 and HP9000/785/C3750, both machines set the Q bit from 0 to 1 without exception. This makes HP-UX 10.20 progress a little bit further. Signed-off-by: Sven Schnelle Message-Id: <20190129191402.29539-1-svens@stackframe.org> [rth: Add a comment to the code as well.] Signed-off-by: Richard Henderson --- target/hppa/op_helper.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'target') diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 912e8d5..6bf478e 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -665,11 +665,15 @@ void HELPER(reset)(CPUHPPAState *env) target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) { target_ulong psw = env->psw; - /* ??? On second reading this condition simply seems - to be undefined rather than a diagnosed trap. */ - if (nsm & ~psw & PSW_Q) { - hppa_dynamic_excp(env, EXCP_ILL, GETPC()); - } + /* + * Setting the PSW Q bit to 1, if it was not already 1, is an + * undefined operation. + * + * However, HP-UX 10.20 does this with the SSM instruction. + * Tested this on HP9000/712 and HP9000/785/C3750 and both + * machines set the Q bit from 0 to 1 without an exception, + * so let this go without comment. + */ env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); return psw & PSW_SM; } -- cgit v1.1