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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:05:38 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 15:17:56 -0800 |
| commit | c1027460dcbb782ea69a2c2d2dd8c53b4b3a625f (patch) | |
| tree | 67da442572779199c7877ebc0fc51c59523eac8f /target/riscv/cpu.c | |
| parent | 6ad831ebf142ba971c5e4cb29c52b1c0c92c259b (diff) | |
| download | qemu-c1027460dcbb782ea69a2c2d2dd8c53b4b3a625f.zip qemu-c1027460dcbb782ea69a2c2d2dd8c53b4b3a625f.tar.gz qemu-c1027460dcbb782ea69a2c2d2dd8c53b4b3a625f.tar.bz2 | |
target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
Only V extension supports EEW = 64 in these cases: Zve64* extensions don't
support EEW = 64 in these cases as commented before the check.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-14-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv/cpu.c')
0 files changed, 0 insertions, 0 deletions