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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:05:37 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 15:17:55 -0800 |
| commit | 6ad831ebf142ba971c5e4cb29c52b1c0c92c259b (patch) | |
| tree | c4550f399d882d6d79606331b033b291d30afb7f /target/riscv/cpu.c | |
| parent | e80865e5f36e6bb38eae551ecb09f069b9e21e93 (diff) | |
| download | qemu-6ad831ebf142ba971c5e4cb29c52b1c0c92c259b.zip qemu-6ad831ebf142ba971c5e4cb29c52b1c0c92c259b.tar.gz qemu-6ad831ebf142ba971c5e4cb29c52b1c0c92c259b.tar.bz2 | |
target/riscv: Fix check for vector load/store instructions when EEW=64
The V extension supports all vector load and store instructions except
the V extension does not support EEW=64 for index values when XLEN=32.
(Section 18.3)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-13-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv/cpu.c')
0 files changed, 0 insertions, 0 deletions