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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-05-12 15:41:00 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-05-18 11:32:41 +0100 |
| commit | f8977d50fc43176ca33796e36e7cd40e809c3628 (patch) | |
| tree | cd0ccc545bbc1c3ced8bb45c8165cc2ffb4107e3 /target/arm | |
| parent | 6201b2a4d050548731eae88c770106352271749e (diff) | |
| download | qemu-f8977d50fc43176ca33796e36e7cd40e809c3628.zip qemu-f8977d50fc43176ca33796e36e7cd40e809c3628.tar.gz qemu-f8977d50fc43176ca33796e36e7cd40e809c3628.tar.bz2 | |
target/arm: Convert CBZ, CBNZ to decodetree
Convert the compare-and-branch-immediate insns CBZ and CBNZ
to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-15-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/tcg/a64.decode | 5 | ||||
| -rw-r--r-- | target/arm/tcg/translate-a64.c | 26 |
2 files changed, 11 insertions, 20 deletions
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 483e364..f5759a6 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -113,3 +113,8 @@ EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 B 0 00101 .......................... @branch BL 1 00101 .......................... @branch + +%imm19 5:s19 !function=times_4 +&cbz rt imm sf nz + +CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f702e9b..06619f8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1334,33 +1334,22 @@ static bool trans_BL(DisasContext *s, arg_i *a) return true; } -/* Compare and branch (immediate) - * 31 30 25 24 23 5 4 0 - * +----+-------------+----+---------------------+--------+ - * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | - * +----+-------------+----+---------------------+--------+ - */ -static void disas_comp_b_imm(DisasContext *s, uint32_t insn) + +static bool trans_CBZ(DisasContext *s, arg_cbz *a) { - unsigned int sf, op, rt; - int64_t diff; DisasLabel match; TCGv_i64 tcg_cmp; - sf = extract32(insn, 31, 1); - op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ - rt = extract32(insn, 0, 5); - diff = sextract32(insn, 5, 19) * 4; - - tcg_cmp = read_cpu_reg(s, rt, sf); + tcg_cmp = read_cpu_reg(s, a->rt, a->sf); reset_btype(s); match = gen_disas_label(s); - tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, + tcg_gen_brcondi_i64(a->nz ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, match.label); gen_goto_tb(s, 0, 4); set_disas_label(s, match); - gen_goto_tb(s, 1, diff); + gen_goto_tb(s, 1, a->imm); + return true; } /* Test and branch (immediate) @@ -2408,9 +2397,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) static void disas_b_exc_sys(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 7)) { - case 0x1a: case 0x5a: /* Compare & branch (immediate) */ - disas_comp_b_imm(s, insn); - break; case 0x1b: case 0x5b: /* Test & branch (immediate) */ disas_test_b_imm(s, insn); break; |