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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-05-12 15:40:59 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-05-18 11:32:22 +0100 |
| commit | 6201b2a4d050548731eae88c770106352271749e (patch) | |
| tree | e7d1cb59f81158906203f2dd6ffaa548f8af8e91 /target/arm | |
| parent | 4240fb6175ea824f5c65cd346bd4086dd92353c2 (diff) | |
| download | qemu-6201b2a4d050548731eae88c770106352271749e.zip qemu-6201b2a4d050548731eae88c770106352271749e.tar.gz qemu-6201b2a4d050548731eae88c770106352271749e.tar.bz2 | |
target/arm: Convert unconditional branch immediate to decodetree
Convert the unconditional branch immediate insns B and BL to
decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-14-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/tcg/a64.decode | 9 | ||||
| -rw-r--r-- | target/arm/tcg/translate-a64.c | 29 |
2 files changed, 19 insertions, 19 deletions
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index e6e1a5f..483e364 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -21,6 +21,7 @@ &ri rd imm &rri_sf rd rn imm sf +&i imm ### Data Processing - Immediate @@ -104,3 +105,11 @@ UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 + +# Branches + +%imm26 0:s26 !function=times_4 +@branch . ..... .......................... &i imm=%imm26 + +B 0 00101 .......................... @branch +BL 1 00101 .......................... @branch diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f939f6c..f702e9b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1319,24 +1319,19 @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, * match up with those in the manual. */ -/* Unconditional branch (immediate) - * 31 30 26 25 0 - * +----+-----------+-------------------------------------+ - * | op | 0 0 1 0 1 | imm26 | - * +----+-----------+-------------------------------------+ - */ -static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) +static bool trans_B(DisasContext *s, arg_i *a) { - int64_t diff = sextract32(insn, 0, 26) * 4; - - if (insn & (1U << 31)) { - /* BL Branch with link */ - gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); - } + reset_btype(s); + gen_goto_tb(s, 0, a->imm); + return true; +} - /* B Branch / BL Branch with link */ +static bool trans_BL(DisasContext *s, arg_i *a) +{ + gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); reset_btype(s); - gen_goto_tb(s, 0, diff); + gen_goto_tb(s, 0, a->imm); + return true; } /* Compare and branch (immediate) @@ -2413,10 +2408,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) static void disas_b_exc_sys(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 7)) { - case 0x0a: case 0x0b: - case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ - disas_uncond_b_imm(s, insn); - break; case 0x1a: case 0x5a: /* Compare & branch (immediate) */ disas_comp_b_imm(s, insn); break; |