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| author | Julia Suvorova <jusual@mail.ru> | 2018-08-14 17:17:19 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-14 17:17:19 +0100 |
| commit | c4379b4874f4c522f6818f1720f295205d7cf34d (patch) | |
| tree | dcd5e13c26673e0a97d93aefdf75e5ca0c0d4ff1 /include/hw/intc | |
| parent | 22ab3460017cfcfb6b50f05838ad142e08becce5 (diff) | |
| download | qemu-c4379b4874f4c522f6818f1720f295205d7cf34d.zip qemu-c4379b4874f4c522f6818f1720f295205d7cf34d.tar.gz qemu-c4379b4874f4c522f6818f1720f295205d7cf34d.tar.bz2 | |
nvic: Change NVIC to support ARMv6-M
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
Signed-off-by: Julia Suvorova <jusual@mail.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/intc')
| -rw-r--r-- | include/hw/intc/armv7m_nvic.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 8bc2911..a472c9b 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -57,6 +57,7 @@ typedef struct NVICState { VecInfo sec_vectors[NVIC_INTERNAL_VECTORS]; /* The PRIGROUP field in AIRCR is banked */ uint32_t prigroup[M_REG_NUM_BANKS]; + uint8_t num_prio_bits; /* v8M NVIC_ITNS state (stored as a bool per bit) */ bool itns[NVIC_MAX_VECTORS]; |