From 7ef0eb35a4e6961d7e40f03f16ed241c95ae93f9 Mon Sep 17 00:00:00 2001 From: Song Gao Date: Thu, 6 Apr 2023 15:11:31 +0800 Subject: hw/intc: Add NULL pointer check on LoongArch ipi device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When ipi mailbox is used, cpu_index is decoded from iocsr register. cpu maybe does not exist. This patch adds NULL pointer check on ipi device. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230512100421.1867848-4-gaosong@loongson.cn> --- hw/intc/trace-events | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/intc/trace-events') diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 50cadfb..5c6094c 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -292,6 +292,7 @@ sh_intc_set(int id, int enable) "setting interrupt group %d to %d" # loongarch_ipi.c loongarch_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64 loongarch_ipi_write(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64 +loongarch_ipi_unsupported_cpuid(const char *s, uint32_t cpuid) "%s unsupported cpuid 0x%" PRIx32 # loongarch_pch_pic.c loongarch_pch_pic_irq_handler(int irq, int level) "irq %d level %d" -- cgit v1.1