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2025-01-27[RISCV] Renaming muladdi to muliadd as per v0.5 spec. (#124237)quic_hchandel1-2/+2
muliadd is more relevant to the operation performed, i.e. multiply by immediate. The latest spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest
2025-01-23[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)quic_hchandel1-1/+3
This extension adds eight 48 bit load store instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2025-01-13[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)quic_hchandel1-1/+2
This extension adds eleven instructions to accelerate interrupt servicing. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2025-01-07[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)quic_hchandel1-2/+3
The Qualcomm uC Xqcicm extension adds 13 conditional move instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2025-01-03[RISCV] Add support of Sdext,Sdtrig extentions (#120936)Shao-Ce SUN1-0/+2
`Sdext` and `Sdtrig` are RISC-V extensions related to debugging. The full specification can be found at https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf
2025-01-03[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)Sudharsan Veeravalli1-1/+3
This extension adds 12 instructions that conditionally load an immediate value. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
2024-12-29[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension ↵quic_hchandel1-2/+3
(#121037) This extension adds 3 instructions that perform load-store address calculation. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com> Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2024-12-16[RISCV] Add ISAInfoTest tests for a few XQCI extensions (#120060)Sudharsan Veeravalli1-8/+6
Missed out adding rv32 only support test checks for a few of the extensions.
2024-12-14[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)Sudharsan Veeravalli1-0/+1
This extension adds 6 instructions that can do multi-word load/store. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
2024-12-12[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)quic_hchandel1-0/+1
The Qualcomm uC Xqcics extension adds 8 conditional select instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2024-12-01[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)Sudharsan Veeravalli1-0/+6
This extension adds 11 instructions that perform integer arithmetic. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
2024-11-29[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)Sudharsan Veeravalli1-0/+6
This extension adds 8 load/store instructions with a scaled index addressing mode. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
2024-11-28[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)Sudharsan Veeravalli1-0/+1
The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and write CSRs. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
2024-11-27[RISCV] Support `svukte` extension (#115657)Brandon Wu1-0/+1
This is the extension for "Address-Independent Latency of User-Mode Faults to Supervisor Addresses". Spec: https://github.com/riscv/riscv-isa-manual/pull/1564, https://lf-riscv.atlassian.net/browse/RVS-2977 The spec states that the `svukte` depends on `sv39`, but we don't have `sv39` yet, so I didn't add it to the implied list.
2024-11-22[RISCV] Make A implies Zaamo and Zalrsc (#116907)Jim Lin1-8/+27
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc.
2024-11-21[RISCV] Fix typo in RISCVISAInfoTest.cpp. NFC.Jim Tsung-Chun Lin1-2/+2
ExtsRV32G -> ExtsRV64G.
2024-11-12[RISCV] Zabha/Zacas implies Zaamo (#115694)Jim Lin1-10/+0
The Zabha/Zacas extension depends upon the Zaamo extension. Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc.
2024-11-08[RISCV] Add Smdbltrp and Ssdbltrp extension (#111837)T-Tie1-0/+2
Smdbltrp and Ssdbltrp supports are added in this PR. Specification link(Smdbltrp) : [https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc](url) Specification link(Ssdbltrp) : [https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc](url)
2024-10-29[RISCV] Allow crypto features to imply dependents (#112659)Jubilee1-53/+15
This relationship is a logical dependency. Note Zvbc and Zvknhb. They are explicitly called out in the spec as requiring 64 bits: - https://github.com/riscv/riscv-crypto/blob/56ed7952d13eb5bdff92e2b522404668952f416d/doc/vector/riscv-crypto-spec-vector.adoc
2024-10-29[RISCV] Mark RVB23U64 and RVB23S64 as non-experimental (#113918)Alex Bradbury1-2/+2
The specification was recently ratified <https://github.com/riscv/riscv-profiles/blob/main/src/rvb23-profile.adoc>.
2024-10-28[RISCV] Mark the RVA23S64 and RVA23U64 profiles as non-experimental (#113826)Alex Bradbury1-4/+4
All of the extensions used by these profile are themselves non-experimental, and RVA23 was just ratified <https://riscv.org/announcements/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/>. <https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc> We lack a way of expressing `Ss1p13` (supervisor architecture 1.13), but this is a problem we have for RVA22 (Ss1p12) and RVA20 (Ss1p11) so I don't feel it's a blocker.
2024-10-28[RISCV]Add svvptc extension (#113882)dong-miao1-0/+1
2024-10-28[RISCV] Add the Sha extension (#113820)Alex Bradbury1-0/+1
This was introduced in the now-ratified RVA23 profile (and also added to the RVA22 text) as a simple way of referring to H plus the set of supervisor extensions required by RVA23. https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc This patch simply defines the extension. The next patch will adjust the RVA23 profile to use it, and at that point I think we will be ready to mark RVA23 as non-experimental. Note that I haven't made it so if you enable all extensions that constitute Sha, Sha is implied. Per #76893 (adding 'B'), the concern is making this implication might break older external assemblers. Perhaps this is less of a concern given the relative frequency of `-march=${foo}_zba_zbb_zbs` vs the collection of H extensions. If we did want to add that implication, we'd probably want to add it in a separate patch so it can be easily reverted if found to cause problems.
2024-10-25[RISCV] Mark pointer masking extensions as non-experimental (#113618)Alex Bradbury1-5/+5
These extensions were ratified very recently. <https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+Extensions> I've ensured we have definitions for all extensions in the document <https://drive.google.com/file/d/159QffOTbi3EEbdkKndYRZ2c46D25ZLmO/view?usp=drive_link>. There are no additional CSRs.
2024-10-25[RISCV] Add Smrnmi extension (#111668)dong-miao1-0/+1
This commit has completed the Extension for Resumable Non Maskable Interrupts, adding four CRSs and one Trap-Return instruction. Specification link:["Smrnmi" Extension](https://github.com/riscv/riscv-isa-manual/blob/main/src/rnmi.adoc) --------- Co-authored-by: Sam Elliott <sam@lenary.co.uk>
2024-09-25[RISCV] Mark Zacas as non-experimental (#109651)Alex Bradbury1-1/+1
The extension has been ratified for some time, but we kept it experimental (see #99898) due to <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>. The ABI issue has been resolved by #101023 so I believe there's no known barrier to moving Zacas to non-experimental.
2024-08-21[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)Craig Topper1-0/+2
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3
2024-08-21[RISCV] Remove experimental for Ssqosid ext (#105476)Shao-Ce SUN1-1/+1
Ratified: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
2024-08-19[RISCV] Make extension names lower case in RISCVISAInfo::checkDependency() ↵Craig Topper1-3/+3
error messages.
2024-08-19[RISCV] Merge some ISA error reporting together and make some errors more ↵Craig Topper1-7/+7
precise. Loop over the extension names that have the same error message. Print the name of Zvk* extensions instead of 'zvk*'.
2024-08-18[RISCV] Add more tests for RISCVISAInfo::checkDependency(). NFCCraig Topper1-0/+88
2024-08-19[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)Pengcheng Wang1-0/+2
These two extensions add addtional instructions for carryless multiplication with 32-bits elements and Vector-Scalar GCM instructions. Please see https://github.com/riscv/riscv-isa-manual/pull/1306.
2024-07-23[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)Alex Bradbury1-1/+1
As discussed at the last sync-up call, mark Zacas as experimental until this ABI issue is resolved <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>. Don't return Zacas in getHostCPUFeatures (leaving a TODO there) as even if requesting detection of "native" features, the user likely doesn't want to automatically opt in to experimental codegen.
2024-07-16[RISCV] Bump the version of Zicfilp/Zicfiss to 1.0 (#98891)Yeting Kuo1-4/+4
Both of them are ratified now. https://wiki.riscv.org/display/HOME/Ratified+Extensions This patch does not set them to non-experimental, since Zicfilp lacks lld support and Zicfiss also lacks compiler-rt/libunwind support.
2024-07-11[RISCV][NFC] Add a newline when using --print-enabled-extensions (#98425)Shao-Ce SUN1-1/+2
The `--print-enabled-extensions` has been introduced in the https://github.com/llvm/llvm-project/pull/98207 , but it seems to be missing a newline in the end.
2024-07-11[RISCV] Add QingKe "XW" compressed opcode extension (#97925)R1-0/+1
This extension consists of 8 additional 16-bit compressed forms for existing standard load/store opcodes. These opcodes are found in some RISC-V microcontrollers from WCH / Nanjing Qinheng Microelectronics. As discussed in the Discourse forums, this uses incompatible extension and opcode names vs the vendor binary toolchain. The chosen names instead follow the conventions for other vendor extensions listed on the "riscv-non-isa" project.
2024-07-10[RISCV] Add ability to list extensions enabled for a target (#98207)Michael Maitland1-1/+30
bb83a3d introduced `--print-enabled-extensions` command line option for AArch64. This patch introduces RISC-V support for this option. This patch adds documentation for this option. `riscvExtensionsHelp` is renamed to `printSupportedExtensions` to by synonymous with AArch64 and so it is clear what that function does.
2024-07-09Reapply "[RISCV] Remove experimental from Ztso. (#96465)"Philip Reames1-23/+22
This was reverted in f985a8826bfa4ca3d23e654185de35e30ea6dc79. Since that, the default WMO lowering has moved to A67 compatible, the ABI attribute emission has landed (off by default), and the LLD change to merge said attributes have landed. Our ztso lowering is believed to also be A67 compatible, and no known issues remain. Original commit message: Ztso 1.0 was ratified in January 2023. Documentation: https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc
2024-07-09[RISCV] Remove experimental for bf16 extensions (#97996)Jianjian Guan1-3/+3
They are already ratified now.
2024-07-02[RISCV] Remove IgnoreUnknown from RISCVISAInfo::parseArchString. (#97372)Craig Topper1-48/+0
This isn't used in tree, and thus I don't know what the expectations for its behavior really are. The original usage of this feature has been replaced by parseNormalizedArchString.
2024-06-27[RISCV] Bump Pointer Masking extension version (#96715)Michael Maitland1-5/+5
These extensions had their version number bumped and still experimental (under public review). I didn't see anything in the [commit history](https://github.com/riscv/riscv-j-extension/commits/master/) since #79929 that would warrant a change to the implementation of pointer masking in the compiler.
2024-06-24Revert "[RISCV] Remove experimental from Ztso. (#96465)"Philip Reames1-23/+23
This reverts commit 9cd6ef4b8a5c843ef491437c765d4cb2ff2f8fe3. See discussion on review thread.
2024-06-24[RISCV] Remove experimental from Ztso. (#96465)Yingwei Zheng1-23/+23
Ztso 1.0 was ratified in January 2023. Documentation: https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc
2024-06-21[RISCV] Make M imply Zmmul (#95070)Jianjian Guan1-11/+21
According to the spec, M implies Zmmul.
2024-06-12[RISCV] Add Smcsrind and Sscsrind extension (#93952)Monad1-0/+2
Specification link: https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc Some CSRs (`*ireg` and `*iselect`) in Smcsrind/Sscsrind extensions are originally defined as part of the Smaia/Ssaia extensions and are already supported in LLVM. The missing CSRs (`*ireg2` to `*ireg6` for `m`, `s`, and `vs`) are added in this PR.
2024-06-12[RISCV] Add smcdeleg and ssccfg extensions (#95163)Monad1-0/+2
Specification: https://github.com/riscv/riscv-isa-manual/blob/main/src/smcdeleg.adoc `Ssccfg` introduces one new CSR `scountinhibit`.
2024-06-11[RISCV] Add B extension (#76893)Pengcheng Wang1-7/+2
It seems that we have `B` extension again: https://github.com/riscv/riscv-b According to the spec, `B` extension represents the collection of the `Zba`, `Zbb`, `Zbs` extensions. Though it hasn't been ratified, I set its version to `1.0`.
2024-06-03[RISCV] Remove experimental from Zabha (#93831)AlexGhiti1-1/+1
The Zabha extension was ratified in April 2024. Co-authored-by: Alexandre Ghiti <alexghiti@rivosinc.com>
2024-05-21[RISCV] Bump Zaamo and Zalrsc to version 1.0 (#91556)Brandon Wu1-2/+2
The ratified information can be found here: https://wiki.riscv.org/display/HOME/Ratified+Extensions
2024-05-15[RISCV] Gate unratified profiles behind -menable-experimental-extensions ↵Alex Bradbury1-2/+11
(#92167) As discussed in the last sync-up call, because these profiles are not yet finalised they shouldn't be exposed to users unless they opt-in to them (much like experimental extensions). We may later want to add a more specific flag, but reusing `-menable-experimental-extensions` solves the immediate problem. This is implemented using the new support for marking profiles s experimental added in #91993 to move the unratified profiles to RISCVExperimentalProfile and making the necessary changes to logic in RISCVISAInfo to handle this.
generated by cgit v1.1 at 2025-09-30 00:23:04 +0000