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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2024-11-28 12:46:15 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-28 12:46:15 +0530 |
| commit | c4645ffedacad18e4cd1dd372288aa55178b1c44 (patch) | |
| tree | c498fc477687e92f8069fb208882dd22f56a8b3f /llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | |
| parent | 9ea5be639d31560faec993b4aebb3e10c7d4c8e2 (diff) | |
| download | llvm-c4645ffedacad18e4cd1dd372288aa55178b1c44.zip llvm-c4645ffedacad18e4cd1dd372288aa55178b1c44.tar.gz llvm-c4645ffedacad18e4cd1dd372288aa55178b1c44.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)
The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Diffstat (limited to 'llvm/unittests/TargetParser/RISCVISAInfoTest.cpp')
| -rw-r--r-- | llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 0694d09..4b450e2 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1104,6 +1104,7 @@ Experimental extensions smctr 1.0 ssctr 1.0 svukte 0.3 + xqcicsr 0.2 Supported Profiles rva20s64 |