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| author | quic_hchandel <165007698+hchandel@users.noreply.github.com> | 2025-01-23 10:14:25 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-23 10:14:25 +0530 |
| commit | 163935a48df69bde944fae2b4581541dab30c730 (patch) | |
| tree | 245858613552f5c5c31219ce7fcd5b3a96f5b7af /llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | |
| parent | aa273fd83eccb55215f4cb18285f8462a1013f5c (diff) | |
| download | llvm-163935a48df69bde944fae2b4581541dab30c730.zip llvm-163935a48df69bde944fae2b4581541dab30c730.tar.gz llvm-163935a48df69bde944fae2b4581541dab30c730.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)
This extension adds eight 48 bit load store instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Diffstat (limited to 'llvm/unittests/TargetParser/RISCVISAInfoTest.cpp')
| -rw-r--r-- | llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 3a7ea45..14a60c1 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -656,7 +656,8 @@ TEST(ParseArchString, RejectsConflictingExtensions) { for (StringRef Input : {"rv64i_xqcisls0p2", "rv64i_xqcia0p2", "rv64i_xqciac0p2", "rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2", - "rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p2"}) { + "rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p2", + "rv64i_xqcilo0p2"}) { EXPECT_THAT( toString(RISCVISAInfo::parseArchString(Input, true).takeError()), ::testing::EndsWith(" is only supported for 'rv32'")); @@ -1122,6 +1123,7 @@ Experimental extensions xqcics 0.2 xqcicsr 0.2 xqciint 0.2 + xqcilo 0.2 xqcilsm 0.2 xqcisls 0.2 |