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48 hours[CostModel][X86] getShuffleCost - SK_Transpose v4f64/v4i64 matches UNPCK - do...Simon Pilgrim1-6/+6
2 days[AArch64] Tweak fixed-length loop.dependence.mask costs (#175538)Benjamin Maxwell1-8/+8
2 days[RISCV] Add cost for @llvm.vector.splice.{left,right} (#179219)Luke Lau2-40/+388
2 days[RISCV][TTI] Adjust the cost of `llvm.abs` intrinsic when `Zvabd` existsPengcheng Wang1-0/+36
5 days[AArch64][SDAG] Legalise BSWAP for Neon types. (#179702)Ricardo Jesus1-1/+1
6 days[ARM] Set operation action for UMULO and SMULO as Custom if not Thumb1 (#154253)SiliconA-Z1-48/+48
6 daysIR: Promote "denormal-fp-math" to a first class attribute (#174293)Matt Arsenault1-2/+2
8 days[Analysis][CostModel] Add insert-extract runlines for Apple CPUs (NFC) (#179236)Tomer Shafir1-11/+11
9 days[CostModel][X86] clmul.ll - add i16 and 128/256/512-bit vector cost tests (#1...Simon Pilgrim1-1/+79
10 days[Analysis] Add Intrinsics::CLMUL case to cost calculations to getIntrinsicIns...niqiangpro-cell2-0/+43
2026-01-27[RISCV] Set the reciprocal throughtput cost for division to TTI::TCC_Expensiv...Ryan Buchner1-252/+252
2026-01-27[TTI] Add VectorInstrContext for context-aware insert/extract costs. (#175982)Florian Hahn1-0/+22
2026-01-26Add quotes around "print<cost-model>" argumentWalter Lee1-1/+1
2026-01-24X86: Fix VSCALE insert element crash in codegen (#177705)ChaseYalon1-0/+10
2026-01-23[AArch64] Add some basic i128 arithmetic cost test cases. NFCDavid Green1-0/+50
2026-01-21[IR] Allow non-constant offsets in @llvm.vector.splice.{left,right} (#174693)Luke Lau3-3/+24
2026-01-20[PowerPC] cost modeling for length type VP intrinsic load/store (#168938)RolandF771-0/+321
2026-01-20[RISCV] Fix i64 gather/scatter cost on rv32 (#176105)Luke Lau2-134/+66
2026-01-17[AArch64] Remove AdjustCost from getCastInstrCost. (#143073)David Green21-1378/+1378
2026-01-16[AArch64] Treat LD1 as cheap in getVectorInstrCostHelper on Apple cores. (#17...Florian Hahn1-22/+43
2026-01-15[RISCV] Add tests for rv32 gather/scatter costs. NFCLuke Lau4-225/+500
2026-01-07[RISCV] Improve cost modeling of RISCVTTIImpl::getConstantPoolLoadCost() (#17...Ryan Buchner1-0/+37
2026-01-06[IR] Split vector.splice into vector.splice.left and vector.splice.right (#17...Luke Lau4-365/+365
2025-12-16[CodeGen] expand-fp: Change frem expansion criterion (#158285)Frederik Harwath4-173/+173
2025-12-15[AArch64] use `isTRNMask` to calculate shuffle costs (#171524)Philip Ginsbach-Chen1-0/+252
2025-12-12[Analysis][AArch64] Add cost model for loop.dependence.{war/raw}.mask (#167551)Sam Tebbs1-0/+189
2025-12-09[IR][RISCV] Remove @llvm.experimental.vp.splat (#171084)Luke Lau1-151/+0
2025-12-06[RISCV][TTI] Add cost model for ROTL/ROTR (#170824)Sudharsan Veeravalli1-0/+181
2025-12-01[RISCV] Rename SFB Base Feature (#169607)Sam Elliott1-1/+1
2025-11-30[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#169890)Shih-Po Hung1-65/+65
2025-11-28[AArch64] Add costs for ROTR and ROTL. (#169335)David Green2-54/+54
2025-11-24[AArch64] Update costs for fshl/r and add rotr/l variants. NFCDavid Green2-256/+790
2025-11-21AMDGPU: Improve getShuffleCost accuracy for 8- and 16-bit shuffles (#168818)Nicolai Hähnle1-488/+498
2025-11-20AMDGPU: Expand cost model shufflevector test (#168816)Nicolai Hähnle1-0/+50
2025-11-18[AArch64] - Improve costing for Identity shuffles for SVE targets. (#165375)Pawan Nirpal1-0/+12
2025-11-17[CostModel][AArch64] Remove promotion cost for SVE bfloat arith supported wit...Benjamin Maxwell1-15/+33
2025-11-11[AArch64][CostModel] Add SVE bfloat arithmetic tests (NFC) (#166951)Benjamin Maxwell1-1/+129
2025-11-10[RISCV][TTI] Fix crash of non-built-in vector type cost quering. (#167258)Elvis Wang1-0/+10
2025-11-07[AArch64][CostModel] Replace undef with poison in sve-arith-fp.ll (NFC) (#166...Benjamin Maxwell1-134/+134
2025-11-04AArch64: Regenerate cost model testsMatt Arsenault1-5/+5
2025-11-04BasicTTI: Cleanup multiple result intrinsic handling (#165970)Matt Arsenault1-4/+17
2025-11-04[AArch64] Improve the cost model for extending mull (#125651)David Green1-126/+126
2025-11-03[AArch64] Remove old non-power2 aarch64-sve-vector-bits-min tests. NFCDavid Green2-22/+0
2025-10-31[CostModel][AArch64] Model cost of extract.last.active intrinsic (clastb) (#1...Graham Hunter1-0/+216
2025-10-24[AArch64][CostModel] Reduce cost of wider than legal get.active.lane.mask (#1...Kerry McLaughlin1-25/+56
2025-10-24[ARM] Update remaining cost tests with -cost-kind=all. NFCDavid Green16-2247/+1908
2025-10-23[ARM] Update more MVE costmodel tests with -cost-kind=all. NFCDavid Green6-804/+597
2025-10-23[Analysis][test] Remove unsafe-fp-math uses (NFC) (#164605)paperchalice1-4/+2
2025-10-20[IR] Replace alignment argument with attribute on masked intrinsics (#163802)Nikita Popov19-3038/+3038
2025-10-15[CostModel] Generate test checks (NFC)Nikita Popov1-9/+16
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