aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-12-09Revert "[LV] Mark checks as never succeeding for high cost cutoff."Aiden Grossman1-5/+1
2025-12-09[LV] Mark checks as never succeeding for high cost cutoff.Florian Hahn1-1/+5
2025-12-09[LV][NFC] Use foldTailWithEVL() (#171282)Pengcheng Wang1-1/+1
2025-12-09[LV] Return getPredBlockCostDivisor in uint64_tLuke Lau1-2/+2
2025-12-08[LV] Compare induction start values via SCEV in assertion (NFCI).Florian Hahn1-1/+4
2025-12-08[VPlan] Use BlockFrequencyInfo in getPredBlockCostDivisor (#158690)Luke Lau1-34/+62
2025-12-07[VPlan] Replace ExtractLast(Elem|LanePerPart) with ExtractLast(Lane/Part) (#1...Florian Hahn1-3/+8
2025-12-04[VPlan] Remove VPWidenRecipe constructor with no underlying instruction. NFCI...Luke Lau1-3/+3
2025-12-02[LV] Use forced cost once for whole interleave group in legacy costmodel (#16...Florian Hahn1-2/+12
2025-12-02[VPlan] Sink predicated stores with complementary masks. (#168771)Florian Hahn1-0/+1
2025-11-29[VPlan] Skip cost verification for loops with EVL gather/scatter.Florian Hahn1-11/+23
2025-11-28[LV] Vectorize selecting last IV of min/max element. (#141431)Florian Hahn1-4/+16
2025-11-28[TTI][Vectorize] Migrate masked/gather-scatter/strided/expand-compress costin...Shih-Po Hung1-4/+9
2025-11-26Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding....Florian Hahn1-1/+2
2025-11-26Revert "Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-...Florian Hahn1-2/+1
2025-11-26Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding....Florian Hahn1-1/+2
2025-11-26[LV] Use VPReductionRecipe for partial reductions (#147513)Sam Tebbs1-15/+25
2025-11-26[VPlan] Hoist predicated loads with complementary masks. (#168373)Florian Hahn1-0/+1
2025-11-24[LV] Count cost of middle block if TC <= VF. (#168949)Florian Hahn1-3/+14
2025-11-24[IVDesc] Make getCastInsts return an ArrayRef (NFC) (#169021)Ramkumar Ramachandra1-2/+1
2025-11-22[VPlan] Create resume phis in scalar preheader early. (NFC) (#166099)Florian Hahn1-14/+3
2025-11-20[VPlan] Remove PtrIV::IsScalarAfterVectorization, use VPlan analysis. (#168289)Florian Hahn1-10/+5
2025-11-20[LV] Check full partial reduction chains in order. (#168036)Florian Hahn1-26/+36
2025-11-20[LV] Allow partial reductions with an extended bin op (#165536)Sam Tebbs1-3/+18
2025-11-19[VPlan] Collect FMFs for in-loop reduction chain in VPlan. (NFC)Florian Hahn1-7/+14
2025-11-19[LV] Consolidate shouldOptimizeForSize and remove unused BFI/PSI. NFC (#168697)Luke Lau1-51/+38
2025-11-19[LV]: Skip Epilogue scalable VF greater than RemainingIterations. (#156724)Hassnaa Hamdi1-7/+18
2025-11-19[TTI] Use MemIntrinsicCostAttributes for getMaskedMemoryOpCost (#168029)Shih-Po Hung1-2/+4
2025-11-18[VPlan] Populate and use VPIRFlags from initial VPInstruction. (#168450)Florian Hahn1-15/+20
2025-11-17[VPlan] Populate and use VPIRMetadata from VPInstructions (NFC) (#167253)Florian Hahn1-19/+20
2025-11-17Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)Ramkumar Ramachandra1-3/+12
2025-11-15[LV] Use VPlan pattern matching in adjustRecipesForReductions (NFC)Florian Hahn1-4/+1
2025-11-14Revert "[VPlan] Expand WidenInt inductions with nuw/nsw" (#168080)Alex Bradbury1-12/+3
2025-11-14[VPlan] Expand WidenInt inductions with nuw/nsw (#163538)Ramkumar Ramachandra1-3/+12
2025-11-14[LV] Explicitly disable in-loop reductions for AnyOf and FindIV. nfc (#163541)Mel Chen1-1/+6
2025-11-14[VPlan] Disable partial reductions again with EVL tail folding (#167863)Luke Lau1-1/+3
2025-11-13Revert "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. ...Florian Hahn1-2/+1
2025-11-13[LV] Update LoopVectorizationPlanner::emitInvalidCostRemarks to handle reduct...Ryan Buchner1-0/+3
2025-11-12[VPlan] Get opcode & type from recipe in adjustRecipesForReduction (NFC)Florian Hahn1-3/+4
2025-11-12[VPlan] Don't look up recipe for IV step via RecipeBuilder. (NFC)Florian Hahn1-14/+8
2025-11-12[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)Florian Hahn1-1/+2
2025-11-12[VPlan] Plumb scalable register size through narrowInterleaveGroups (#167505)Luke Lau1-1/+3
2025-11-11[VPlan] Remove unneeded getDefiningRecipe with isa/cast/dyn_cast. (NFC)Florian Hahn1-4/+2
2025-11-11[VPlan] Add getSingleUser helper (NFC).Florian Hahn1-15/+12
2025-11-11[LV] Consider interleaving when -enable-wide-lane-mask=true (#163387)Kerry McLaughlin1-1/+28
2025-11-11[LV] Move condition to VPPartialReductionRecipe::execute (#166136)Sander de Smalen1-8/+1
2025-11-10[VPlan] Don't apply predication discount to non-originally-predicated blocks ...Luke Lau1-7/+37
2025-11-09[VPlan] Use VPInstructionWithType for casts in VPlan0. (NFC)Florian Hahn1-1/+2
2025-11-07[VPlan] Update more VPRecipeBuilder members to take VPInst directly (NFC)Florian Hahn1-106/+115
2025-11-06[LV] Check all users of partial reductions in chain have same scale. (#162822)Florian Hahn1-8/+25
generated by cgit v1.1 at 2026-01-10 20:57:13 +0000