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path: root/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
AgeCommit message (Expand)AuthorFilesLines
2020-01-21[RISCV] Check the target-abi module flag matches the optionZakk Chen1-2/+12
2020-01-14CMake: Make most target symbols hidden by defaultTom Stellard1-1/+1
2019-12-19[RISCV] Enable the machine outliner for RISC-Vlewis-revill1-0/+3
2019-12-17[RISCV] Add subtargets initialized with target featureZakk Chen1-2/+25
2019-11-13Sink all InitializePasses.h includesReid Kleckner1-0/+1
2019-08-20[RISCV GlobalISel] Adding initial GlobalISel infrastructureDaniel Sanders1-0/+29
2019-08-15[llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere1-1/+1
2019-06-21[RISCV] Add RISCV-specific TargetTransformInfoSam Elliott1-1/+8
2019-06-11Revert CMake: Make most target symbols hidden by defaultTom Stellard1-1/+1
2019-06-10CMake: Make most target symbols hidden by defaultTom Stellard1-1/+1
2019-05-15[RISCV] Create a TargetInfo header. NFCRichard Trieu1-0/+1
2019-03-09[RISCV] Support -target-abi at the MC layer and for codegenAlex Bradbury1-1/+1
2019-02-19[RISCV][NFC] Move some std::string to StringRefAlex Bradbury1-1/+1
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-12-07[Targets] Add errors for tiny and kernel codemodel on targets that don't supp...David Green1-7/+1
2018-09-19[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32AAlex Bradbury1-0/+10
2018-06-27[RISCV] Add machine function pass to merge base + offsetSameer AbuAsal1-0/+5
2018-06-13[RISCV] Codegen support for atomic operations on RV32IAlex Bradbury1-0/+6
2018-03-24[RISCV] Use init_array instead of ctors for RISCV target, by defaultMandeep Singh Grang1-1/+2
2018-01-10[RISCV] Implement support for the BranchRelaxation passAlex Bradbury1-0/+3
2017-11-16[RISCV] Fix 64-bit data layout mismatch between backend and target descriptionMandeep Singh Grang1-1/+1
2017-10-19[RISCV] Initial codegen support for ALU operationsAlex Bradbury1-2/+24
2017-10-12Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun1-3/+3
2017-10-12TargetMachine: Merge TargetMachine and LLVMTargetMachineMatthias Braun1-3/+3
2017-08-03Delete Default and JITDefault code modelsRafael Espindola1-3/+10
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth1-1/+1
2017-05-30TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFCMatthias Braun1-1/+1
2017-02-14[RISCV] Fix RV32 datalayout string and ensure initAsmInfo is calledAlex Bradbury1-2/+4
2016-11-01[RISCV] Add stub backendAlex Bradbury1-0/+58
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