diff options
| author | lewis-revill <lewis.revill@embecosm.com> | 2019-12-19 16:41:53 +0000 |
|---|---|---|
| committer | lewis-revill <lewis.revill@embecosm.com> | 2019-12-19 16:41:53 +0000 |
| commit | a116f28a0d71c221c1dc023908b180beaf22799d (patch) | |
| tree | b82fee045e7cb6c303572bf631938fcd08f85be4 /llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | |
| parent | ba430f503244d1498529d47f31090cdf79b5c231 (diff) | |
| download | llvm-a116f28a0d71c221c1dc023908b180beaf22799d.zip llvm-a116f28a0d71c221c1dc023908b180beaf22799d.tar.gz llvm-a116f28a0d71c221c1dc023908b180beaf22799d.tar.bz2 | |
[RISCV] Enable the machine outliner for RISC-V
This patch enables the machine outliner for RISC-V and adds the
necessary logic for checking whether sequences can be safely outlined,
and describing how they should be outlined. Outlined functions are
called using the register t0 (x5) as the return address register, which
must be available for an occurrence of a sequence to be safely outlined.
Differential Revision: https://reviews.llvm.org/D66210
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 5dcbfdc..54c9826 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -66,6 +66,9 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique<RISCVELFTargetObjectFile>()) { initAsmInfo(); + + // RISC-V supports the MachineOutliner. + setMachineOutliner(true); } const RISCVSubtarget * |