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2025-08-03MCSymbolELF: Migrate away from classofFangrui Song1-2/+2
The object file format specific derived classes are used in context where the type is statically known. We don't use isa/dyn_cast and we want to eliminate MCSymbol::Kind in the base class.
2025-07-15MCFixup: Replace getTargetKind with getKindFangrui Song1-1/+1
2025-07-14[RISCV] Fix QC.E.LI -> C.LI with Bare Symbol Compression (#146763)Sam Elliott1-0/+3
There's a long comment explaining this approach in RISCVInstrInfoXqci.td This change also fixes some problems when fixups are able to be resolved for `qc.e.li` and `qc.li`.
2025-06-20[RISCV] Add symbol parsing support for XAndesPerf branch instructions (#137748)Jim Lin1-0/+2
This patch adds support for parsing symbols in the XAndesPerf branch immediate instructions. The branch immediate instructions use `R_RISCV_NDS_BRANCH_10` relocation. It uses a 10-bit PC-relative branch offset.
2025-06-16[RISCV] Rename Relocation QC_E_JUMP_PLT to QC_E_CALL_PLT (#143998)Sam Elliott1-2/+2
The semantics and definition of this relocation are unchanged. The new name reflects that instructions with the relocation should be assumed to clobber non-callee-saved registers, as with the R_RISCV_CALL_PLT relocation. The name was changed in v0.2 of the ABI extensions: https://github.com/quic/riscv-elf-psabi-quic-extensions/releases/tag/v0.2
2025-06-15RISCV: Move RISCVMCExpr functions to RISCVMCAsmInfo or RISCVMCAsmBackendFangrui Song1-3/+3
* Move getPCRelHiFixup closer to the only caller RISCVAsmBackend::evaluateTargetFixup. * Declare getSpecifierForName in RISCVMCAsmInfo, in align with other targets that have migrated to the new relocation specifier representation.
2025-06-07RISCVMCExpr: Migrate to MCSpecifierExprFangrui Song1-9/+5
2025-05-24MCELFObjectTargetWriter::needsRelocateWithSymbol: Remove MCSymbol argumentFangrui Song1-2/+1
Replace MCSymbol argument with MCValue::AddSym. The minor difference in .weakref handling is negligible, as our implementation may not fully align with GAS, and .weakref is not used in practice.
2025-05-24ELFObjectWriter: Remove the MCContext argument from getRelocTypeFangrui Song1-4/+3
Additionally, swap MCFixup/MCValue order to match addReloc/recordRelocation.
2025-05-24ELFObjectWriter: Replace Ctx.reportError with reportErrorFangrui Song1-7/+6
Prepare for removing MCContext from getRelocType functions.
2025-05-24MCFixup: Remove FK_PCRel_ from getKindForSizeFangrui Song1-1/+0
Remove FK_PCRel_* kinds from the generic fixup list, as they are not generic like FK_Data_*. In getRelocType, FK_PCRel_* can be replaced with FK_Data_* by leveraging the IsPCRel argument. Their inclusion in the generic kind list caused confusion for PowerPC, RISCV, and VE targets. The X86/M68k uses can be implemented as target-specific fixups.
2025-05-17RISCV: Replace most Specifier constants with relocation typesFangrui Song1-15/+12
... as they map directly and we don't utilize -Wswitch. Retained VK_*_LO constants for lowering to LO_I or LO_S. The Sparc port has eliminated all Specifier constants (commit 003fa7731d81a47c98e9c55f80d509933c9b91f6), and the LoongArch port is nearly free of them (#138632). Pull Request: https://github.com/llvm/llvm-project/pull/138644
2025-04-18MCFixup: Move relocation values before FK_NONEFangrui Song1-1/+1
Simplify the process of encoding a raw relocation type using MCFixupKind. Currently, FirstRelocationkind is utilized by AArch64, LoongArch, and RISCV.
2025-04-18MCFixup: Add isRelocation/isRelocRelocation helpersFangrui Song1-1/+1
Add two helper functions to simplify checks for relocation types, replacing direct comparisons with FirstRelocationKind and FirstLiteralRelocationKind. Note: Some targets haven't utilized isRelocation yet. Also, update RelaxFixupKind to use 0 as the sentinel value.
2025-04-17[RISCV] Simplify fixup kinds that force relocationsFangrui Song1-33/+5
For RELA targets, fixup kinds that force relocations (GOT, TLS, ALIGN, RELAX, etc) can bypass `applyFixup` and be encoded as `FirstRelocationKind+i`, as seen in LoongArch. This patch removes redundant fixup kinds and adopts the `FirstRelocationKind+i` encoding. The `llvm-mc -show-encoding` output no longer displays descriptive fixup names, as this information is removed from `RISCVAsmBackend::getFixupKindInfo`. While a backend hook could be added to call `llvm::object::getELFRelocationTypeName`, it's unnecessary since the relocation in `-filetype=obj` output is what truly matters. Pull Request: https://github.com/llvm/llvm-project/pull/136088
2025-04-12ELFObjectWriter: Make .reloc test genericFangrui Song1-3/+0
Move `Fixup.getKind() >= FirstLiteralRelocationKind` from target hooks to ELFObjectWriter::recordRelocation. Currently, getRelocType cannot be skipped for LoongArch due to #135519
2025-04-11[RISCV] Add symbol parsing support for Xqcilb long branch instructions (#135044)Sudharsan Veeravalli1-0/+2
This patch adds support for parsing symbols in the Xqcilb long branch instructions. The instructions use the `R_RISCV_QC_E_JUMP_PLT` relocation and the `InstFormatQC_EJ` instruction format. Vendor relocation support will be added in a later patch.
2025-04-08[RISCV] Add symbol parsing support for Xqcili load large immediate ↵Sudharsan Veeravalli1-0/+4
instructions (#134581) This patch adds support for parsing symbols in the Xqcili load large immediate instructions. The 32 bit `qc.li` instructions uses the `R_RISCV_QC_ABS20_U` relocation while the 48 bit `qc.e.li` instruction uses the `R_RISCV_QC_E_32` relocation and the `InstFormatQC_EAI` instruction format. Vendor relocation support will be added in a later patch.
2025-04-06MCValue: Replace getRefKind with getSpecifierFangrui Song1-1/+1
2025-04-05MCValue: Store SymA specifier at SpecifierFangrui Song1-3/+0
The relocation specifier should be accessed via MCValue::Specifier. However, some targets encode the relocation specifier within SymA using MCSymbolRefExpr::SubclassData and access it via getAccessVariant(), though this method is now deprecated. This change stores the SymA specifier at Specifier as well, unifying the two code paths. * CSKY: GOT- and PLT- relocations now suppress the STT_SECTION conversion. * AArch64: https://reviews.llvm.org/D156505 added `getRefkind` check to prevent folding. This is a hack and is now removed. MCValue: Unify relocation specifier storage by storing SymA specifier at Specifier The relocation specifier is accessed via MCValue::Specifier, but some targets encoded it within SymA using MCSymbolRefExpr::SubclassData and retrieved it through the now-deprecated getAccessVariant() method. This commit unifies the two approaches by storing the SymA specifier at `Specifier` as well. Additional changes: - CSKY: GOT- and PLT- relocations now suppress STT_SECTION conversion. - AArch64: Removed the `getRefkind` check hack (introduced in https://reviews.llvm.org/D156505) that prevented folding. Removed the assertion from `getRelocType`. - RISCV: Removed the assertion from `getRelocType`. Future plans: - Replace MCSymbolRefExpr members with MCSymbol within MCValue. - Remove `getSymSpecifier` (added for migration).
2025-04-05[MC] Replace getSymA()->getSymbol() with getAddSym. NFCFangrui Song1-3/+3
We will replace the MCSymbolRefExpr member in MCValue with MCSymbol. This change reduces dependence on MCSymbolRefExpr.
2025-04-05[MC] Replace getSpecifier(Target.getSymA()) with Target.getSymSpecifier()Fangrui Song1-1/+1
Add MCValue::getSymSpecifier as a workaround for targets that encode the relocation specifier on SymA. This function asserts that SymA is not null.
2025-04-04[RISCV] Add symbol parsing support for the Xqcibi branch immediate ↵Sudharsan Veeravalli1-0/+2
instructions (#134233) This patch adds support for parsing symbols in the Xqcibi branch immediate instructions. While the 32 bit branch instructions use the same instruction format and relocation as the existing branch instructions in RISCV, the 48 bit ones use the `InstFormatQC_EB` instruction format and the `R_RISCV_QC_E_BRANCH` relocation that is defined in `BinaryFormat/ELFRelocs/RISCV_nonstandard.def.` Vendor relocation support will be added in a later patch.
2025-03-29[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrelFangrui Song1-9/+28
clang -fexperimental-relative-c++-abi-vtables might generate `@plt` and `@gotpcrel` specifiers in data directives. The syntax is not used in humand-written assembly code, and is not supported by GNU assembler. Note: the `@plt` in `.word foo@plt` is different from the legacy `call func@plt` (where `@plt` is simply ignored). The `@plt` syntax was selected was simply due to a quirk of AsmParser: the syntax was supported by all targets until I updated it to be an opt-in feature in a0671758eb6e52a758bd1b096a9b421eec60204c RISC-V favors the `%specifier(expr)` syntax following MIPS and Sparc, and we should follow this convention. This PR adds support for `.word %pltpcrel(foo+offset)` and `.word %gotpcrel(foo)`, and drops `@plt` and `@gotpcrel`. * MCValue::SymA can no longer have a SymbolVariant. Add an assert similar to that of AArch64ELFObjectWriter.cpp before https://reviews.llvm.org/D81446 (see my analysis at https://maskray.me/blog/2025-03-16-relocation-generation-in-assemblers if intrigued) * `jump foo@plt, x31` now has a different diagnostic. Pull Request: https://github.com/llvm/llvm-project/pull/132569
2025-03-22[RISCV] Move VK_GOTPCREL and VK_PLT to RISCVMCExpr::SpecifierFangrui Song1-2/+2
to migrate away from the deprecated MCSymbolRefExpr::VariantKind. In the future, @GOTPCREL and @PLT in data directives should be encoded as part of RISCVMCExpr instead of MCSymbolRefExpr.
2025-03-20[RISCV] Rename VariantKind to SpecifierFangrui Song1-1/+1
Follow the X86 and Mips renaming. > "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation. > "Relocation specifier" is clear, aligns with Arm and IBM AIX's documentation, and fits the assembler's role seamlessly. In addition, rename *MCExpr::getKind, which confusingly shadows the base class getKind.
2025-03-17Rename RISCVMCExpr::VK_RISCV_ to VK_. NFCFangrui Song1-5/+5
They implement relocation operators and are named VK_RISCV_ probably to avoid confusion with `MCSymbolRefExpr::VariantKind`. `MCSymbolRefExpr::VariantKind` is discouraged (https://discourse.llvm.org/t/error-expected-relocatable-expression-with-mctargetexpr/84926/2) and targets are migrating away from `MCSymbolRefExpr::VariantKind`. Therefore, there is no need to make the name long in the presence of the clear `RISCVMCExpr::` prefix. Pull Request: https://github.com/llvm/llvm-project/pull/131489
2025-03-15[RISCV] Move fixELFSymbolsInTLSFixups to getRelocTypeFangrui Song1-0/+11
fixELFSymbolsInTLSFixups walks the expression tree, which is complex and unnecessary. As the expression must be relocatable, we can move the code to getRelocType and just set SymA. The behavior is similar to GNU assembler.
2024-01-23[RISCV] Support TLSDESC in the RISC-V backend (#66915)Paul Kirth1-0/+15
This patch adds basic TLSDESC support in the RISC-V backend. Specifically, we add new relocation types for TLSDESC, as prescribed in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373, and add a new pseudo instruction to simplify code generation. This patch does not try to optimize the local dynamic case, which can be improved in separate patches. Linker side changes will also be handled separately. The current implementation is only enabled when passing the new `-enable-tlsdesc` codegen flag.
2024-01-10[llvm][lld] Support R_RISCV_GOT32_PCREL (#72587)PiJoules1-0/+2
This is the followup implementation to https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/402 that supports this relocation in llvm and lld.
2023-08-29[MC,AArch64] Suppress local symbol to STT_SECTION conversion for GOT relocationsFangrui Song1-1/+1
Assemblers change certain relocations referencing a local symbol to reference the section symbol instead. This conversion is disabled for many conditions (`shouldRelocateWithSymbol`), e.g. TLS symbol, for most targets (including AArch32, x86, PowerPC, and RISC-V) GOT-generating relocations. However, AArch64 encodes the GOT-generating intent in MCValue::RefKind instead of MCSymbolRef::Kind (see commit 0999cbd0b9ed8aa893cce10d681dec6d54b200ad (2014)), therefore not affected by the code `case MCSymbolRefExpr::VK_GOT:`. As GNU ld and ld.lld create GOT entries based on the symbol, ignoring addend, the two ldr instructions will share the same GOT entry, which is not expected: ``` ldr x1, [x1, :got_lo12:x] // converted to .data+0 ldr x1, [x1, :got_lo12:y] // converted to .data+4 .data // .globl x, y would suppress STT_SECTION conversion x: .zero 4 y: .long 42 ``` This patch changes AArch64 to suppress local symbol to STT_SECTION conversion for GOT relocations, matching most other targets. x and y will use different GOT entries, which IMO is the most sensable behavior. With this change, the ABI decision on https://github.com/ARM-software/abi-aa/issues/217 will only affect relocations explicitly referencing STT_SECTION symbols, e.g. ``` ldr x1, [x1, :got_lo12:(.data+0)] ldr x1, [x1, :got_lo12:(.data+4)] // I consider this unreasonable uses ``` IMO all reasonable use cases are unaffected. Link: https://github.com/llvm/llvm-project/issues/63418 GNU assembler PR: https://sourceware.org/bugzilla/show_bug.cgi?id=30788 Reviewed By: peter.smith Differential Revision: https://reviews.llvm.org/D158577
2023-08-09[RISCV] Remove unneeded fixup kinds for R_RISCV_{SET,ADD,SUB}*Fangrui Song1-42/+0
These 8/16/32/64 fixup kinds from D103539 are no longer needed after D155357. R_RISCV_SET6/R_RISCV_SUB6 are unneeded even before D155357. `return Value & 0x03` is incorrect, and the non-zero TargetOffset is probably to affect applyFixup, but the relevant code is dead as Value == 0.
2023-03-27[RISCV] Replace RISCV -> RISC-V in comments. NFCCraig Topper1-1/+1
To be consistent with RISC-V branding guidelines https://riscv.org/about/risc-v-branding-guidelines/ Think we should be using RISC-V where possible. More patches will follow. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146449
2023-03-06RISCVELFObjectWriter: de-capitalize some error messagesFangrui Song1-2/+2
These are unfortunately untested. I'll add some tests in a subsequent change.
2023-02-23[MC][CodeGen] Define R_RISCV_PLT32 and lower dso_local_equivalent to itLeonard Chan1-1/+4
This introduces R_RISCV_PLT32, PC-relative data relocation that takes the 32-bit relative offset to a function or its PLT entry from its relocation location. This is needed to support relative vtables on RISCV. Github PR: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/363 The lld handling of this reloc is D143115. Differential Revision: https://reviews.llvm.org/D143226
2022-09-13[RISCV] Assemble `call foo` to R_RISCV_CALL_PLTFangrui Song1-1/+1
R_RISCV_CALL/R_RISCV_CALL_PLT distinction isn't necessary. R_RISCV_CALL has been deprecated as a resolution to https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/98 . ld.lld and mold treat the two relocation types the same. GNU ld has a custom handling for undefined weak functions which is unnecessary: calling an unresolved undefined weak function is UB and GNU ld can handle the case without a relocation error (such a function call is usually guarded by a zero value check and should be allowed). This patch assembles `call foo` to use R_RISCV_CALL_PLT instead of the deprecated R_RISCV_CALL. Note: the code generator still differentiates `call foo` and (maybe preemptible) `call foo@plt`, but the difference is purely aesthetic. Note: D105429 does not support R_RISCV_CALL_PLT correctly. Changed the test to force R_RISCV_CALL for now. Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D132530
2022-02-06[llvm] Use = default (NFC)Kazu Hirata1-1/+1
2021-06-17RISCV: adjust handling of relocation emission for RISCVSaleem Abdulrasool1-20/+42
This re-architects the RISCV relocation handling to bring the implementation closer in line with the implementation in binutils. We would previously aggressively resolve the relocation. With this restructuring, we always will emit a paired relocation for any symbolic difference of the type of S±T[±C] where S and T are labels and C is a constant. GAS has a special target hook controlled by `RELOC_EXPANSION_POSSIBLE` which indicates that a fixup may be expanded into multiple relocations. This is used by the RISCV backend to always emit a paired relocation - either ADD[WIDTH] + SUB[WIDTH] for text relocations or SET[WIDTH] + SUB[WIDTH] for a debug info relocation. Irrespective of whether linker relaxation support is enabled, symbolic difference is always emitted as a paired relocation. This change also sinks the target specific behaviour down into the target specific area rather than exposing it to the shared relocation handling. In the process, we also sink the "special" handling for debug information down into the RISCV target. Although this improves the path for the other targets, this is not necessarily entirely ideal either. The changes in the debug info emission could be done through another type of hook as this functionality would be required by any other target which wishes to do linker relaxation. However, as there are no other targets in LLVM which currently do this, this is a reasonable thing to do until such time as the code needs to be shared. Improve the handling of the relocation (and add a reduced test case from the Linux kernel) to ensure that we handle complex expressions for symbolic difference. This ensures that we correct relocate symbols with the adddends normalized and associated with the addition portion of the paired relocation. This change also addresses some review comments from Alex Bradbury about the relocations meant for use in the DWARF CFA being named incorrectly (using ADD6 instead of SET6) in the original change which introduced the relocation type. This resolves the issues with the symbolic difference emission sufficiently to enable building the Linux kernel with clang+IAS+lld (without linker relaxation). Resolves PR50153, PR50156! Fixes: ClangBuiltLinux/linux#1023, ClangBuiltLinux/linux#1143 Reviewed By: nickdesaulniers, maskray Differential Revision: https://reviews.llvm.org/D103539
2020-04-10[MC][RISCV] Make .reloc support arbitrary relocation typesFangrui Song1-0/+2
Similar to D76746 (ARM), D76754 (AArch64) and llvmorg-11-init-6967-g152d14da64c (x86) Differential Revision: https://reviews.llvm.org/D77018
2019-12-19[RISCV] Don't crash on unsupported relocationsLuís Marques1-2/+11
Summary: Instead of crashing due to the `llvm_unreachable`, provide a proper error when invalid fixups/relocations are encountered. Reviewers: asb, lenary Reviewed By: asb Tags: #llvm Differential Revision: https://reviews.llvm.org/D71536
2019-08-23[MC] Minor cleanup to MCFixup::Kind handling. NFC.Sam Clegg1-1/+1
Prefer `MCFixupKind` where possible and add getTargetKind() to convert to `unsigned` when needed rather than scattering cast operators around the place. Differential Revision: https://reviews.llvm.org/D59890 llvm-svn: 369720
2019-08-20[RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for ↵Alex Bradbury1-0/+5
the FDE location Follow binutils in using RISCV_32_PCREL for the FDE initial location. As explained in the relevant binutils commit <https://github.com/riscv/riscv-binutils-gdb/commit/a6cbf936e3dce68114d28cdf60d510a3f78a6d40>, the ADD/SUB pair of relocations is problematic in the presence of linker relaxation. This patch has the same end goal as D64715 but includes test changes and avoids adding a new global VariantKind to MCExpr.h (preferring RISCVMCExpr VKs like the rest of the RISC-V backend). Differential Revision: https://reviews.llvm.org/D66419 llvm-svn: 369375
2019-08-15[llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere1-1/+1
Now that we've moved to C++14, we no longer need the llvm::make_unique implementation from STLExtras.h. This patch is a mechanical replacement of (hopefully) all the llvm::make_unique instances across the monorepo. llvm-svn: 369013
2019-07-19[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.Hsiangkai Wang1-0/+4
It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366524
2019-07-18Revert "[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame."Hsiangkai Wang1-4/+0
This reverts commit 17e3cbf5fe656483d9016d0ba9e1d0cd8629379e. llvm-svn: 366444
2019-07-18[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.Hsiangkai Wang1-0/+4
It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366442
2019-07-16[RISCV] Make RISCVELFObjectWriter::getRelocType check IsPCRelAlex Bradbury1-25/+36
Previously, this function didn't check the IsPCRel argument. But doing so is a useful check for errors, and also seemingly necessary for FK_Data_4 (which we produce a R_RISCV_32_PCREL relocation for if IsPCRel). Other than R_RISCV_32_PCREL, this should be NFC. Future exception handling related patches will include tests that capture this behaviour. llvm-svn: 366172
2019-04-23[RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiersLewis Revill1-0/+4
This patch adds support for parsing and assembling the %tls_ie_pcrel_hi and %tls_gd_pcrel_hi modifiers. Differential Revision: https://reviews.llvm.org/D55342 llvm-svn: 358994
2019-04-04[RISCV] Support assembling TLS add and associated modifiersLewis Revill1-0/+8
This patch adds support in the MC layer for parsing and assembling the 4-operand add instruction needed for TLS addressing. This also involves parsing the %tprel_hi, %tprel_lo and %tprel_add operand modifiers. Differential Revision: https://reviews.llvm.org/D55341 llvm-svn: 357698
2019-04-02[RISCV] Support assembling @plt symbol operandsAlex Bradbury1-0/+2
This patch allows symbols appended with @plt to parse and assemble with the R_RISCV_CALL_PLT relocation. Differential Revision: https://reviews.llvm.org/D55335 Patch by Lewis Revill. llvm-svn: 357470
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