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2 hours[RISCV] Add commutative support for Qualcomm uC Xqcicm extension (#160653)HEADmainquic_hchandel2-2/+63
This is a follow-up to #145643. See https://github.com/llvm/llvm-project/pull/145643#issuecomment-3009300419.
13 hours[RISCV][NFC] Rename getOppositeBranchCondition (#160972)Sam Elliott3-6/+6
14 hours[RISCV] Teach getIntImmCostInst about (X & -(1 << C1) & 0xffffffff) == C2 << ↵Craig Topper1-0/+39
C1 (#160163) We can rewrite this to (srai(w)/srli X, C1) == C2 so the AND immediate is free. This transform is done by performSETCCCombine in RISCVISelLowering.cpp. This fixes the opaque constant case mentioned in #157416.
3 daysRevert "[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470)"ShihPo Hung4-35/+0
This reverts commit aa08b1a9963f33ded658d3ee655429e1121b5212.
4 days[ASan][RISCV] Teach AddressSanitizer to support indexed load/store. (#160443)Hank Chang1-0/+38
This patch is based on https://github.com/llvm/llvm-project/pull/159713 This patch extends AddressSanitizer to support indexed/segment instructions in RVV. It enables proper instrumentation for these memory operations. A new member, `MaybeOffset`, is added to `InterestingMemoryOperand` to describe the offset between the base pointer and the actual memory reference address. Co-authored-by: Yeting Kuo <yeting.kuo@sifive.com>
4 days[RISCV] Update SiFive7's scheduling models with their optimizations on ↵Min-Yih Hsu1-10/+94
permutation instructions (#160763) In newer SiFIve7 cores like X390, permutation instructions like vrgather.vv operates on LMUL smaller than a single DLEN could yield a constant cycle. For slightly larger data that fits in the constraint of `log2(SEW/8) + log2(LMUL) <= log2(DLEN / 32)`, these instructions can also yield cycles that are proportional to the quadratic of LMUL, rather than being proportional to VL. Co-authored-by: Michael Maitland <michaeltmaitland@gmail.com>
4 days[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470)Shih-Po Hung4-0/+35
Split out from #151300 to isolate TargetTransformInfo cost modelling for fault-only-first loads from VPlan implementation details. This change adds costing support for vp.load.ff independently of the VPlan work. For now, model a vp.load.ff as cost-equivalent to a vp.load.
6 days[RISCV] Set riscv-fpimm-cost threshold to 3 by default (#159352)Alex Bradbury1-1/+1
`-riscv-fp-imm-cost` controls the threshold at which the constant pool is used for float constants rather than generating directly (typically into a GPR followed by an `fmv`). The value used for this knob indicates the number of instructions that can be used to produce the value (otherwise we fall back to the constant pool). Upping to to 3 covers a huge number of additional constants (see <https://github.com/llvm/llvm-project/issues/153402>), e.g. most whole numbers which can be generated through lui+shift+fmv. As in general we struggle with efficient code generation for constant pool accesses, reducing the number of constant pool accesses is beneficial. We are typically replacing a two-instruction sequence (which includes a load) with a three instruction sequence (two simple arithmetic operations plus a fmv), which. The CHECK prefixes for various tests had to be updated to avoid conflicts leading to check lines being dropped altogether (see <https://github.com/llvm/llvm-project/pull/159321> for a change to update_llc_test_checks to aid diagnosing this).
6 days[RISCV] Disable slideup optimization on the inconsistent element type of ↵Hongyu Chen1-0/+8
EVec and ContainerVT (#159373) Fixes https://github.com/llvm/llvm-project/issues/159294 The element type of EVecContainerVT and ContainerVT can be different after promoting integer types. This patch disables the slideup optimization in that case.
6 days[RISCV] Don't merge pseudo selects with stack adjustment instrs in between ↵Elizaveta Noskova1-2/+6
(#160105) When we have sequence of select pseudo instructions with stack adjustment instructions in between, we shouldn't apply the optimization, proposed by link https://reviews.llvm.org/D59355. If optimization is applied, function won't be marked `adjustsStack` during Finalize ISel pass.
6 days[RISCV] Remove bfloat vectors from AllFloatVectors. NFC (#160399)Craig Topper3-78/+90
This removes a bunch of unreachable isel patterns for floating point operations like fadd, fsub, fmul, etc. Eventually we will need patterns for Zvfbfa but this will require new pseudoinstructions with the altfmt bit set so these extra patterns aren't helpful for that either. Add a new AllFloatAndBFloatVectors for the instructions that we do need both for like vrgather, vcompress, vmerge.
6 days[RISCV] Refactor DAG-to-DAG Selection: Port lowering code for ↵quic_hchandel3-99/+86
`qc.insb/qc.insbi` to RISCVISelLowering.cpp (#157618) This is a follow-up to #154135 and does similar changes for `qc.insb/qc.insbi`.
6 days[RISCV] Update SiFive7's scheduling model on mask and data movement ↵Min-Yih Hsu1-4/+14
instructions (#160155) Vector to scalar movement instructions, as well as mask instructions like vcpop and vfirst, should have a higher latency & occupancy on SiFive7. --------- Co-authored-by: Michael Maitland <michaeltmaitland@gmail.com>
6 days[RISCV][NFC] Rename simm12 to simm12_lo (#160380)Sam Elliott8-107/+113
This more closely matches what we have done for uimm20, and should allow us to in future differentiate between places that accept %*lo(expr) and those where that is not allowed. I have not introduced a `simm12` node for the moment, so that downstream users notice the change.
7 days[CodeGen] Rename isReallyTriviallyReMaterializable [nfc]Philip Reames3-4/+4
.. to isReMaterializableImpl. The "Really" naming has always been awkward, and we're working towards removing the "Trivial" part now, so go ehead and remove both pieces in a single rename. Note that this doesn't change any aspect of the current implementation; we still "mostly" only return instructions which are trivial (meaning no virtual register uses), but some targets do lie about that today.
7 days[MCA][RISCV]Enable latency instrument on RISCV (#160063)Roman Belenov1-23/+23
Recently added latency customization ([PR](https://github.com/llvm/llvm-project/pull/155420)) does not work on RISCV since it has target-specific InstrumentManager that overrides default functionality. Added calls to base class to ensure that common instruments (including latency customizer) are available.
7 days[RISCV] Add MC layer support for Andes XAndesVSIntH extension. (#159514)Rux1243-2/+63
Add MC layer support for Andes XAndesVSIntH extension. The spec is available at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release
7 days[TTI][ASan][RISCV] reland Move InterestingMemoryOperand to Analysis and ↵Hank Chang2-0/+80
embed in MemIntrinsicInfo #157863 (#159713) [Previously reverted due to failures on asan-rvv-intrinsics.ll, the test case is riscv only and it is triggered by other target] Reland [#157863](https://github.com/llvm/llvm-project/pull/157863), and add `; REQUIRES: riscv-registered-target` in test case to skip the configuration that doesn't register riscv target. Previously asan considers target intrinsics as black boxes, so asan could not instrument accurate check. This patch make SmallVector<InterestingMemoryOperand> a member of MemIntrinsicInfo so that TTI can make targets describe their intrinsic informations to asan. Note, 1. This patch move InterestingMemoryOperand from Transforms to Analysis. 2. Extend MemIntrinsicInfo by adding a SmallVector<InterestingMemoryOperand> member. 3. This patch does not support RVV indexed/segment load/store.
8 days[TableGen][DecoderEmitter][RISCV] Always handle `bits<0>` (#159951)Sergei Barannikov2-3/+10
Previously, `bits<0>` only had effect if `ignore-non-decodable-operands` wasn't specified. Handle it even if the option was specified. This should allow for a smoother transition to the option removed. The change revealed a couple of inaccuracies in RISCV compressed instruction definitions. * `C_ADDI4SPN` has `bits<5> rs1` field, but `rs1` is not encoded. It should be `bits<0>`. * `C_ADDI16SP` has `bits<5> rd` in the base class, but it is unused since `Inst{11-7}` is overwritten with constant bits. We should instead set `rd = 2` and `Inst{11-7} = rd`. There are a couple of alternative fixes, but this one is the shortest.
8 days[RISCV] Use isUInt<32> instead of <= 0xffffffff. NFCCraig Topper1-1/+1
8 days[RISCV] Use SignExtend64<32> instead of ORing in 32 1s into upper bits in ↵Craig Topper1-4/+4
RISCVMatInt. NFC (#159864) I think this better reflects the intent of modification. In all these places we know bit 31 is 1 so we are sign extending.
8 days[RISCV][NFC] Parsed Immediates are Expressions (#159888)Sam Elliott1-110/+113
I find it very confusing that we have two different kinds of "immediates": - MCOperands in the backend that are `isImm()` which can only be numbers - RISCVOperands in the parser that are `isImm()` which can contain expressions This change aims to make it clearer that in the AsmParser, we are dealing with expressions, rather than just numbers. Unfortunately, `isImm` comes from the `MCParsedAsmOperand`, which is needed for Microsoft Inline Asm, so we cannot fully get rid of it.
10 days[RISCV] Fix typo in comment. NFCCraig Topper1-1/+1
10 days[RISCV] Update comments in RISCVMatInt to reflect we don't always use ADDIW ↵Craig Topper1-14/+15
after LUI now. NFC (#159829) The simm32 base case only uses lui+addiw when necessary after 3d2650bdeb8409563d917d8eef70b906323524ef The worst case 8 instruction sequence doesn't leave a full 32 bits for the LUI+ADDI(W) after the 3 12-bit ADDI and SLLI pairs are created. So we will never generate LUI+ADDIW in the worst case sequence.
11 days[RISCV] Use MutableArrayRef instead of SmallVectorImpl&. NFC (#159651)Craig Topper1-2/+2
We're only going to modify existing items, not add or remove any elements to the vector.
11 days[RISCV] Re-work how VWADD_W_VL and similar _W_VL nodes are handled in ↵Craig Topper1-37/+49
combineOp_VLToVWOp_VL. (#159205) These instructions have one already narrow operand. Previously, we pretended like this operand was a supported extension. This could cause problems when we called getOrCreateExtendedOp on this narrow operand when creating the the VWADD_VL. If the narrow operand happened to be an extend of the opposite type, we would peek through it and then rebuild it with the wrong extension type. So (vwadd_w_vl (i32 (sext X)), (i16 (zext Y))) would become (vwadd_vl (i16 (sext X)), (i16 (sext Y))). To prevent this, we ignore the operand instead and pass std::nullopt for SupportsExt to getOrCreateExtendedOp so it won't peek through any extends on the narrow source. Fixes #159152.
11 days[RISCV] Fix build after e747223c03e16d02cd0dc6f8eedb5c825a7366c1Michael Liao1-2/+2
11 days[NFC][RISCV] Move Zvfbf* relative stuffs to RISCVInstrInfoZvfbf.td (#159619)Brandon Wu5-60/+66
11 daysRISC-V: builtins support for MIPS RV64 P8700 execution control .UmeshKalappa2-1/+8
the following changes are made a)Typo Fix (with previous PRhttps://github.com/llvm/llvm-project/pull/155747) b)builtins support for MIPS P8700 execution control instructions . c)Testcase
11 days[RISCV] Implement MC support for Zvfofp8min extension (#157014)Jim Lin4-4/+45
This patch adds MC support for Zvfofp8min https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp8min.adoc.
11 days[RISCV][GISel] Support select vx, vf form rvv intrinsics (#157398)Jianjian Guan4-2/+51
For vx form, we legalize it with widen scalar. And for vf form, we select the right register bank.
11 days[RISCV] Use Subtarget member variable instead of getting it from ↵Craig Topper1-9/+7
MachineFunction. NFC (#159664)
11 days[RISCV] Ignore debug instructions in RISCVVLOptimizer (#159616)Luke Lau1-1/+2
Don't put them onto the worklist, since they'll crash when we try to check their opcode. Fixes #159422
11 daysRevert "[TTI][ASan][RISCV] Move InterestingMemoryOperand to Analysis and ↵Florian Mayer2-80/+0
embed in MemIntrinsicInfo" (#159700) Reverts llvm/llvm-project#157863
11 days[TTI][ASan][RISCV] Move InterestingMemoryOperand to Analysis and embed in ↵Hank Chang2-0/+80
MemIntrinsicInfo (#157863) Previously asan considers target intrinsics as black boxes, so asan could not instrument accurate check. This patch make SmallVector<InterestingMemoryOperand> a member of MemIntrinsicInfo so that TTI can make targets describe their intrinsic informations to asan. Note, 1. This patch move InterestingMemoryOperand from Transforms to Analysis. 2. Extend MemIntrinsicInfo by adding a SmallVector<InterestingMemoryOperand> member. 3. This patch does not support RVV indexed/segment load/store.
11 days[RISC-V] Add P-ext MC Support for Remaining Pair Operations (#159247)Qihan Cai1-0/+258
This patch implements pages 21-24 from jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf Documentation: jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf Co-authored-by: Craig Topper <craig.topper@sifive.com>
11 days[RISCV] Use bseti 31 for (or X, -2147483648) when upper 32 bits aren't used. ↵Craig Topper1-0/+13
(#159678) If the original type was i32, type legalization will sign extend the constant. This prevents it from having a single bit set or clear so other patterns can't match. If the upper bits aren't used, we can ignore the sign extension. Similar for bclri and binvi.
11 days[RISCV] Move Xqci Select-likes to use riscv_selectcc (#153147)Sam Elliott3-81/+105
The original patterns for the Xqci select-like instructions used `select`, and marked that ISD node as legal. This is not the usual way that `select` is dealt with in the RISC-V backend. Usually on RISC-V, we expand `select` to `riscv_select_cc` which holds references to the operands of the comparison and the possible values depending on the comparison. In retrospect, this is a much better fit for our instructions, as most of them correspond to specific condition codes, rather than more generic `select` with a truthy/falsey value. This PR moves the Xqci select-like patterns to use `riscv_select_cc` nodes. This applies to the Xqcicm, Xqcics and Xqcicli instruction patterns. In order to match the existing codegen, minor additions had to be made to `translateSetCCForBranch` to ensure that comparisons against specific immediate values are left in a form that can be matched more closely by the instructions. This prevents having to insert additional `li` instructions and use the register forms. There are a few slight regressions: - There are sometimes more `mv` instructions than entirely necessary. I believe these would not be seen with larger examples where the register allocator has more leeway. - In some tests where just one of the three extensions is enabled, codegen falls back to using a branch over a move. With all three extensions enabled (the configuration we most care about), these are not seen. - The generated patterns are very similar to each other - they have similar complexity (7 or 8) and there are still overlaps. Sometimes the choice between two instructions can be affected by the order of the patterns in the tablegen file. One other change is that Xqcicm instructions are prioritised over Xqcics instructions where they have identical patterns. This is done because one of the the Xqcicm instructions is compressible (`qc.mveqi`), while none of the Xqcics instructions are.
11 days[RISCV] Pass SDValue by value. NFCCraig Topper1-4/+4
11 days[RISCV] Update the vector integer division cycle in SiFive7 scheduling model ↵Min-Yih Hsu1-2/+5
(#159468) Vector integer division in SiFive7 processes a single bit at a time up to 4 elements. This patch updates to reflect this behavior. Co-authored-by: Michael Maitland <michaeltmaitland@gmail.com>
11 days[RISCV] Update floating point load latency in SiFive7 scheduling model (#159462)Min-Yih Hsu1-10/+8
The latency of floating point loads in SiFive7 should be the same as their integer counterparts. Co-authored-by: Michael Maitland <michaeltmaitland@gmail.com>
12 days[RISCV][GlobalIsel] Remove redundant sext.w for ADDIW (#159597)Shaoce SUN2-0/+5
This is the minimal case generated by clang at `-O0`; I'm not sure if writing the test this way is appropriate.
12 days[RISCV] Add MVendorID, MArchID, and MImpID for sifive-p550. (#159465)Craig Topper1-1/+5
12 days[RISCV] Match fmaxnum and fminnum to reduction ops. (#159244)Jim Lin1-7/+20
This patch tries to match fmaxnum and fminnum to vector reductions.
12 days[RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (#146858)Boyao Wang4-0/+46
This adds the CodeGen support of Zibi v0.1 experimental extension, which depends on #127463.
12 days[RISCV][GISel] Lower G_SSUBE (#157855)woruyu1-1/+1
### Summary Try to implemente Lower G_SSUBE in LegalizerHelper::lower
12 days[RISCV][NFC] Merge some WriteRes entries in SiFive7 scheduling model (#159448)Min-Yih Hsu1-14/+6
NFC.
13 days[RISCV] Add isel for bitcasting between bfloat and half types (#158828)Ying Wang1-0/+7
There is no RISCV isel for bitcast between f16 and bf16 which will trigger "cannot select" fatal error. Co-authored-by: Ying Wang <wy446777@alibaba-inc.com>
13 days[RISCV] Remove unused SDTypeProfile. NFC (#159156)Craig Topper1-3/+0
13 days[RISCV] Implement computeKnownBitsForTargetNode for SHL_ADD (#159105)Piotr Fusik1-0/+10
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