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path: root/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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2017-12-20[AArch64][SVE] Re-submit patch series for ZIP1/ZIP2Sander de Smalen1-0/+20
2017-12-18Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turboReid Kleckner1-20/+0
2017-12-18[AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen1-0/+20
2017-11-29Reverted r319315 because of unused functions (due to PPR not yet beingSander de Smalen1-20/+0
2017-11-29[AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen1-0/+20
2017-11-07[AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing supportFlorian Hahn1-0/+24
2017-08-18[AArch64] Fix for buildbots, unused functionSam Parker1-3/+0
2017-08-18[AArch64] Remove DecodeAuthLoadWritebackSam Parker1-21/+0
2017-08-11[AArch64] Enable ARMv8.3-A pointer authenticationSam Parker1-0/+42
2017-07-25[AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use wa...Eugene Zelenko1-107/+109
2017-07-07Fix some more -Wimplicit-fallthrough warnings. NFCI.Simon Pilgrim1-2/+2
2016-10-09Move the global variables representing each Target behind accessor functionMehdi Amini1-6/+6
2016-08-17Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner1-6/+6
2016-07-15Minor code cleanups. NFC.Junmo Park1-2/+2
2016-07-05AArch64: TableGenerate system instruction operands.Tim Northover1-6/+5
2015-11-26[AArch64] Add ARMv8.2-A UAO PSTATE bitOliver Stannard1-1/+2
2015-10-05[MC layer][AArch64] llvm-mc accepts 4-bit immediate values forAlexandros Lamprineas1-0/+3
2015-09-15Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and r...Daniel Sanders1-4/+5
2015-09-15Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* an...Daniel Sanders1-5/+4
2015-09-15Revert r247684 - Replace Triple with a new TargetTuple ...Daniel Sanders1-4/+5
2015-09-15Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.Daniel Sanders1-5/+4
2015-07-06Change the last few internal StringRef triples into Triple objects.Daniel Sanders1-1/+1
2015-06-02[AArch64] Add v8.1a atomic instructionsVladimir Sukharev1-0/+40
2015-05-13MC: Modernize MCOperand API naming. NFC.Jim Grosbach1-49/+49
2015-04-16[AArch64] Add v8.1a "Limited Ordering Regions" extensionVladimir Sukharev1-0/+8
2015-04-16[AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget fea...Vladimir Sukharev1-1/+4
2015-01-18unique_ptrify the RelInfo parameter to TargetRegistry::createMCSymbolizerDavid Blaikie1-7/+5
2014-11-12Pass an ArrayRef to MCDisassembler::getInstruction.Rafael Espindola1-5/+2
2014-11-10Misc style fixes. NFC.Rafael Espindola1-10/+10
2014-10-01[AArch64] Allow access to all system registers with MRS/MSR instructions.Tom Coxon1-20/+4
2014-09-30[AArch64] Remove unnecessary whitespace. (Test commit)Tom Coxon1-2/+2
2014-09-02Fix left shifts of negative integers in AArch64 InstPrinter/DisassemblerAlexey Samsonov1-3/+3
2014-07-25Run sort_includes.py on the AArch64 backend.Benjamin Kramer1-2/+2
2014-07-23AArch64: remove "arm64_be" support in favour of "aarch64_be".Tim Northover1-6/+2
2014-05-24AArch64/ARM64: move ARM64 into AArch64's placeTim Northover1-0/+1559
2014-05-24AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover1-1572/+0
2014-04-29[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final...Craig Topper1-1/+1
2014-04-22[Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth1-2/+2
2014-04-15[MC] Require an MCContext when constructing an MCDisassembler.Lang Hames1-8/+7
2014-02-24Add AArch64 big endian Target (aarch64_be)Christian Pirker1-1/+3
2014-02-03Remove unnecessary include of AArch64GenInstrInfo.inc from AArch64Disassemble...Craig Topper1-1/+0
2014-01-24Fix known typosAlp Toker1-1/+1
2014-01-07Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth1-4/+4
2013-11-29[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.Kevin Qin1-0/+36
2013-11-28AArch64: Fix a bug about disassembling post-index load single element to 4 ve...Hao Liu1-4/+4
2013-11-25Fixed a bug about disassembling AArch64 post-index load/store single element ...Hao Liu1-9/+14
2013-11-19Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu1-1/+428
2013-11-12[AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalarChad Rosier1-0/+10
2013-11-05Implement AArch64 post-index vector load/store multiple N-element structure c...Hao Liu1-0/+108
2013-10-31[AArch64] Add support for NEON scalar shift immediate instructions.Chad Rosier1-0/+52
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