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| author | Alexey Samsonov <vonosmas@gmail.com> | 2014-09-02 16:19:41 +0000 |
|---|---|---|
| committer | Alexey Samsonov <vonosmas@gmail.com> | 2014-09-02 16:19:41 +0000 |
| commit | 729b12ede3201bd2e78c24bd739884d3bb4cd87d (patch) | |
| tree | 6c6ee80ec0fd15116f5cbcb12d70211acc54959b /llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | |
| parent | bbb3a7f51c45f2956c569798680a37a814561cf7 (diff) | |
| download | llvm-729b12ede3201bd2e78c24bd739884d3bb4cd87d.zip llvm-729b12ede3201bd2e78c24bd739884d3bb4cd87d.tar.gz llvm-729b12ede3201bd2e78c24bd739884d3bb4cd87d.tar.bz2 | |
Fix left shifts of negative integers in AArch64 InstPrinter/Disassembler
Summary:
Left shift of negative integer is an undefined behavior, and
is reported by UBSan. It's ok for imm values to be negative, so we can
just replace left shifts with multiplications.
Test Plan: check-llvm test suite
Reviewers: t.p.northover
Reviewed By: t.p.northover
Subscribers: aemerson, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D5132
llvm-svn: 216910
Diffstat (limited to 'llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 9726b2a..9e86188 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -610,7 +610,7 @@ static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, if (ImmVal & (1 << (19 - 1))) ImmVal |= ~((1LL << 19) - 1); - if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal << 2, Addr, + if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 4)) Inst.addOperand(MCOperand::CreateImm(ImmVal)); return Success; @@ -1506,7 +1506,7 @@ static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, if (imm & (1 << (26 - 1))) imm |= ~((1LL << 26) - 1); - if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4)) + if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) Inst.addOperand(MCOperand::CreateImm(imm)); return Success; @@ -1548,7 +1548,7 @@ static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, else DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); Inst.addOperand(MCOperand::CreateImm(bit)); - if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4)) + if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) Inst.addOperand(MCOperand::CreateImm(dst)); return Success; |