aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/CodeGen/SelectionDAG
AgeCommit message (Expand)AuthorFilesLines
2026-02-12[SelectionDAG] Make sure demanded lanes for AND/MUL-by-zero are frozen (#180727)Björn Pettersson3-10/+29
2026-02-12[DAGCombiner] Fix subvector extraction index for big-endian STLF (#180795)陈子昂1-2/+13
2026-02-12[SDAG] Copy flags in convertMask when legalizing vselect/setcc (#180979)David Green1-1/+2
2026-02-12Reapply "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321) (#180954)sstipano1-2/+2
2026-02-11[Mips] Fix cttz.i32 fails to lower on mips16 (#179633)yingopq1-1/+5
2026-02-10[DAGCombiner] Fix crash in reassociationCanBreakAddressingModePattern for mul...Alexander Weinrauch1-1/+4
2026-02-10[SDAG] Implement missing legalization for `ISD::VECTOR_FIND_LAST_ACTIVE` (#18...Benjamin Maxwell2-0/+48
2026-02-09[TargetLowering] Avoid creating a VTList until we know we need it. NFC (#180599)Craig Topper1-2/+2
2026-02-09[SelectionDAGBuilder] Remove NoNaNsFPMath uses (#169904)paperchalice4-53/+79
2026-02-07Revert "[SelectionDAG] Fix null pointer dereference in resolveDanglingDebugIn...Qinkun Bao1-1/+1
2026-02-07[SelectionDAG] Fix null pointer dereference in resolveDanglingDebugInfo (#174...Haoren Wang1-1/+1
2026-02-06Revert "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321)Vladimir Vereschaka1-4/+2
2026-02-06Add llvm.cond.loop intrinsic.Peter Collingbourne4-0/+26
2026-02-06[MC][TableGen] Expand Opcode field of MCInstrDesc (#179652)sstipano1-2/+4
2026-02-06[DAGCombiner] Look through freeze for ext(freeze(extload(x))) (#178669)David Sherwood1-16/+28
2026-02-06[DAGCombiner] Fix exact power-of-two signed division for large integers (#177...Steffen Larsen1-2/+6
2026-02-05[SelectionDAG] Mark LowerTypeTests as required and remove intrinsic handling ...keremsahn1-1/+2
2026-02-04[SelectionDAG] Add expansion for llvm.modf intrinsic (#179434)Alex Wang1-0/+42
2026-02-04Add SDNodeFlag::NoConvergent (#179323)Stanislav Mekhanoshin2-0/+6
2026-02-04[CodeGen] Remove unused first operand of SUBREG_TO_REG (#179690)Jay Foad1-14/+19
2026-02-04[LegalizeVectorTypes] Don't emit VP_SELECT when widening MLOAD to VP_LOAD (#1...Luke Lau1-3/+6
2026-02-03Reapply "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/Morp...Craig Topper1-8/+17
2026-02-03Revert "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/Morph...Craig Topper1-17/+8
2026-02-03[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/MorphNodeTo i...Craig Topper1-8/+17
2026-02-03[LegalizeTypes] Don't promote operands to VP extends (#179475)Luke Lau2-74/+27
2026-02-03[SelectionDAG] Use promoted types when creating nodes after type legalization...ZhaoQi1-0/+7
2026-02-02[CodeGen] Add getTgtMemIntrinsic overload for multiple memory operands (NFC) ...Nicolai Hähnle5-58/+108
2026-02-02[SelectionDAG][NFC] Rename isConstantSequence to isArithmeticSequence (#179108)Philip Ginsbach-Chen1-1/+1
2026-02-02[SDAG] (abs (add nsw a, -b)) -> (abds a, b) (#175801)DaKnig1-3/+36
2026-02-02[PowerPC] using milicode call for strcmp instead of lib call (#177009)zhijian lin2-5/+13
2026-02-02[DAG] visitVECTOR_SHUFFLE - ensure correct resno when folding shuffle(bop(shu...Simon Pilgrim2-2/+17
2026-02-01[SDAG] Check for `nsz` in DAG.canIgnoreSignBitOfZero() (#178905)Benjamin Maxwell2-9/+10
2026-02-01[Analysis] Add Intrinsics::CLMUL case to cost calculations to getIntrinsicIns...niqiangpro-cell1-0/+3
2026-01-30[SelectionDAGISel] Avoid unnecessary MatchScope copy. NFC (#178957)Craig Topper1-2/+1
2026-01-30[SelectionDAG] Handle undef at any position in isConstantSequence (#176671)Philip Ginsbach-Chen1-14/+47
2026-01-30[SelectionDAGISel] Use size_t for MatcherIndex. NFC (#178828)Craig Topper1-24/+24
2026-01-30[DAG] Reland: Enable bitcast STLF for Constant/Undef (#178890)陈子昂1-3/+26
2026-01-30Revert "[DAG] Enable bitcast STLF for Constant/Undef" (#178872)Alex Bradbury1-26/+3
2026-01-30[DAG] Enable bitcast STLF for Constant/Undef (#172523)陈子昂1-3/+26
2026-01-29SelectionDAG: Add -print-sdnode-addrs flag.Peter Collingbourne1-0/+6
2026-01-29[RISCV] Support ISD::CLMUL/CLMULH for i64 scalable vectors with Zvbc. (#178340)Craig Topper1-2/+6
2026-01-29[AArch64] Optimize memset to use NEON DUP instruction for more sizes (#166030)Osama Abdelkader2-10/+30
2026-01-29[CodeGen] Fix MachineMemOperand Size of MaskedLoad (#156398)Wei Xiao1-1/+1
2026-01-29[SelectionDAG] Add CTLS to FoldConstantArithmetic and optimize i1 CTLS to 0. ...Craig Topper1-0/+9
2026-01-29[LLVM][DAGCombiner] Look through freeze when combining extensions of loads (#...David Sherwood4-20/+49
2026-01-28[CodeGen] Only use actual alloca alignment (#178361)Jameson Nash1-1/+1
2026-01-28[NFC][CodeGen] Use getAllocationSize instead of manual size computation (#178...Jameson Nash1-4/+4
2026-01-28[DAG] SDPatternMatch - allow m_BinOp / m_c_BinOp to take an optional SDNodeFl...Simon Pilgrim1-12/+8
2026-01-28[DAG] SimplifyDemandedBits - ICMP_SLT(X,0) - only sign mask of X is required ...Anikesh Parashar1-16/+28
2026-01-28[LegalizeIntegerTypes] Add `PromoteIntOp_ANY_EXTEND_VECTOR_INREG` (#178144)Abhishek Kaushik2-0/+14
generated by cgit v1.2.3 (git 2.39.1) at 2026-05-15 23:04:45 +0000