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path: root/llvm/lib/CodeGen/SelectionDAG
AgeCommit message (Expand)AuthorFilesLines
2025-12-09[DAGCombiner] Relax nsz constraint for FP optimizations (#165011)Guy David2-6/+51
2025-12-09[SDAG] Don't handle non-canonical libcalls in SDAG lowering (#171114)Nikita Popov1-6/+12
2025-12-09[IR][RISCV] Remove @llvm.experimental.vp.splat (#171084)Luke Lau3-38/+0
2025-12-08[DAG] Generate UMULH/SMULH with wider vector types (#170283)David Green1-6/+5
2025-12-08DAG: Set MachinePointerInfo for stack when expanding divrem libcall (#170537)Matt Arsenault1-2/+5
2025-12-08[DAGCombiner] Don't peek through bitcast when checking isMulAddWithConstProfi...Hongyu Chen1-2/+2
2025-12-05DAG: Add overload of getExternalSymbol using RTLIB::LibcallImpl (#170587)Matt Arsenault4-14/+17
2025-12-05DAG: Avoid asserting on libcall action if function is unavailable (#170585)Matt Arsenault1-7/+13
2025-12-05DAG: Add overload of makeLibCall which calls an RTLIB::LibcallImpl (#170584)Matt Arsenault3-25/+34
2025-12-05[DAG] Fold mul 0 -> 0 when expanding mul into parts. (#168780)David Green1-0/+2
2025-12-04DAG: Avoid using getLibcallName for function support test (#170583)Matt Arsenault3-8/+9
2025-12-04DAG: Use more RTLIB helper functions for getting libcall from type (#170563)Matt Arsenault1-123/+14
2025-12-04[DAGCombiner] Allow promoted constants in MULHU by power-of-2 -> SRL transfor...Valeriy Savchenko1-2/+4
2025-12-04[DAGCombiner] Handle type-promoted constants in SDIV exact lowering (#169950)Valeriy Savchenko1-3/+5
2025-12-04[DAGCombiner] Handle type-promoted constants in SDIV lowering (#169924)Valeriy Savchenko2-5/+9
2025-12-04[DAGCombiner] Handle type-promoted constants in UDIV exact lowering (#169949)Valeriy Savchenko1-3/+5
2025-12-04[IR] Add CallBr intrinsics support (#133907)Robert Imschweiler2-20/+59
2025-12-04expandFMINIMUMNUM_FMAXIMUMNUM: Improve compare between zeros (#140193)YunQiang Su1-6/+13
2025-12-03DAG: Use poison for filler values on legalize error paths (#170556)Matt Arsenault1-2/+2
2025-12-03[DAGCombiner] Handle type-promoted constants in UDIV lowering (#169491)Valeriy Savchenko2-9/+21
2025-12-03DAG: Avoid using getLibcallName when looking for a divrem call (#170413)Matt Arsenault1-2/+13
2025-12-03DAG: Avoid more uses of getLibcallName (#170402)Matt Arsenault2-2/+3
2025-12-03DAG: Use LibcallImpl in various getLibFunc helpers (#170400)Matt Arsenault2-51/+70
2025-12-03[SDAG] Disable illegal extract_subvector splitting for scalable vectors (#170...Benjamin Maxwell1-19/+31
2025-12-02Avoid maxnum(sNaN, x) optimizations / folds (#170181)Lewis Crawford2-8/+11
2025-12-01[LLVM][CodeGen] Remove failure cases when widening EXTRACT/INSERT_SUBVECTOR. ...Paul Walker2-19/+79
2025-12-01[SelectionDAG] Add SelectionDAG::getTypeSize. NFC (#169764)Luke Lau4-61/+39
2025-11-30[DAG] getCarry - always succeed if we encounter a i1 type during trunc/ext pe...Simon Pilgrim1-3/+3
2025-11-28[AArch64][SVE] Add basic support for `@llvm.masked.compressstore` (#168350)Benjamin Maxwell1-12/+15
2025-11-26Add IR and codegen support for deactivation symbols.Peter Collingbourne4-13/+68
2025-11-25[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)Drew Kersnar2-5/+7
2025-11-22[DAGCombiner] Don't optimize insert_vector_elt into shuffle if implicit trunc...Hongyu Chen1-0/+4
2025-11-20[DAGCombiner] Remove unneeded m_BitReverse from visitBITREVERSE. NFC (#168918)Craig Topper1-2/+2
2025-11-20Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#...Matt Arsenault1-6/+10
2025-11-20[SDAG] Fix whitespace errors (NFC) (#168897)Ramkumar Ramachandra2-17/+17
2025-11-20DAG: Fix constructing a temporary TargetTransformInfo instance (#168480)Matt Arsenault3-21/+14
2025-11-19DAG: Use poison for some vector result widening (#168290)Matt Arsenault1-12/+12
2025-11-19CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)Matt Arsenault1-2/+3
2025-11-19DAG: Use poison when splitting vector_shuffle results (#168176)Matt Arsenault1-1/+1
2025-11-19[DAG] Update canCreateUndefOrPoison to handle ISD::VECTOR_COMPRESS (#168010)陈子昂1-0/+3
2025-11-18[RISCV] Legalize misaligned unmasked vp.load/vp.store to vle8/vse8. (#167745)Craig Topper1-2/+9
2025-11-18[DAGCombiner] Fold select into partial.reduce.add operands. (#167857)Sander de Smalen2-14/+59
2025-11-17[DAG] Add strictfp implicit def reg after metadata. (#168282)David Green1-7/+7
2025-11-16Revert "DAG: Allow select ptr combine for non-0 address spaces" (#168292)ronlieb1-10/+6
2025-11-16DAG: Preserve poison in combineConcatVectorOfScalars (#168220)Matt Arsenault1-2/+2
2025-11-16[SelectionDAG] Verify SDTCisVT and SDTCVecEltisVT constraints (#150125)Sergei Barannikov1-0/+116
2025-11-15[SelectionDAG] Fix AArch64 machine verifier bug when expanding LOOP_DEPENDENC...AZero132-2/+2
2025-11-15DAG: Use poison in SplitVecRes_VP_LOAD_FF (#167753)Matt Arsenault1-1/+1
2025-11-15DAG: Use poison when legalizing scalar_to_vector results (#167751)Matt Arsenault1-1/+1
2025-11-14[SelectionDAGBuilder] Propagate fast-math flags to fpext (#167574)Mikołaj Piróg2-2/+7
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